- 119 -
VBAT
PWR
URXD
UTXD
3G
2.5G
GND
RX
TX
UFLS
ON_SW
DIGD
ON BOARD ARM9 JTAG & ETM INTERFACE
LG Electronics
G
RTC
BASE BAND PROCESSOR
DIGC1~2
12
R&D CHK:
MMC
6
Changed by:
7
DIGB
128M SDRAM
9
DIGA
10
VBR
DOC CTRL CHK:
v1.0
12
QA CHK:
DIGC2
Page:
11
PLL
USB
DIGD
DIGC1
JP3
10
EBU
ETM
DIGC1
A
Engineer:
3
Time Changed:
Open
Short
JP2
JP3
7
B
DIGD
JP2
H
Drawn by:
MFG ENGR CHK:
3
Short
Date Changed:
2
JP0
5
D
DIGD
SIM
W.J.KIM
RTC
C
8
1
BB
D
DIGA
DIGD
E
F
TITLE:
E
JP1
C
DIGC1~2
DIGD
DIGD
Open
256M SDRAM
Open
8
REV:
DIGA
G
DIGA
Size:
F
4
Drawing Number:
6
Short
M
Issue 1.0
9
RTC
DIGA
5
BB
DIGC2
INTEL Memory(128SDRAM, 1.8 I/O)
1
H
T.K.CHOI
A
JP0
JP1
4
3:07:35 pm
2005-10-11
mentor
1/5
ME820
12 1 8 A
A3
Open
2
11
B
Short
0.01u
TP129
C114
C103
0.1u
NA
R115
J9
VSS_DSPMAIN2
VSS_DSPMAIN3
J10
VSS_DSPMAIN4
J11
L8
VSS_DSPMAIN5
L9
VSS_DSPMAIN6
VSS_DSPMAIN7
L10
VSS_DSPMAIN8
L11
T12
VSS_PLL_RTC
VSS_USB
R12
L15
VSSBB
VSSBG
N19
VSSD
U16
VSSM
V15
J15
VSSP_DIG1
VSSP_DIG2
E13
VSSP_DIG3
E10
E8
VSSP_DIG4
VSSP_EBU1
J5
M5
VSSP_EBU2
R8
VSSP_EBU3
VSSP_ETM
P5
VSSVBR_1
T17
P17
VSSVBR_2
R16
VSSVBT
J8
VSS_DSPMAIN1
H9
VDD_DSP1
VDD_DSP2
H10
VDD_DSP3
H11
VDD_MAIN1
M9
M10
VDD_MAIN2
K8
VDD_MAIN3
VDD_MAIN4
K9
VDD_MAIN5
K10
K11
VDD_MAIN6
W12
VDD_PLL
VDD_RTC
W13
VDD_USB
W11
VMICN
K16
L16
VMICP
VREFN
P16
VREFP
L17
T14
VDDD
V14
VDDM
G19
VDDP_DIGA
A9
VDDP_DIGB
VDDP_DIGC1
A15
VDDP_DIGC2
B19
B1
VDDP_DIGD
J1
VDDP_EBU1
W2
VDDP_EBU2
VDDP_EBU3
W7
VDDP_ETM
W10
A13
VDDP_MMC
VDDP_SIM
L19
VDDVBR_1
U18
R17
VDDVBR_2
VDDVBT
T15
USART0_CTS_N
G3
H4
USART0_RTS_N
G1
USART0_RXD
USART0_TXD
G4
USART1_CTS_N
F15
E19
USART1_RTS_N
F17
USART1_RXD
USART1_TXD
G18
V11
USB_DMINUS
USB_DPLUS
U11
B7
USIF_RXD_MRST
USIF_SCLK
D9
A7
USIF_TXD_MTSR
K19
VCXO_EN
VDDBB
M15
K17
VDDBG
TRACESYNC
U8
E14
TRIG_IN
C19
TRST_N
B17
T_OUT0
T_OUT1
B16
T_OUT10
A16
C13
T_OUT11
T_OUT12
D17
B15
T_OUT2
T_OUT3
D13
B14
T_OUT4
T_OUT5
C18
D15
T_OUT6
D14
T_OUT7
T_OUT8
A18
C14
T_OUT9
J17
SSC1_MRST
SSC1_MTSR
K18
SSC1_SCLK
H15
TCK
E16
D19
TDI
TDO
E17
TMS
F16
V8
TRACECLK
TRACEPKT0
R9
W9
TRACEPKT1
TRACEPKT2
T10
V9
TRACEPKT3
TRACEPKT4
U10
V10
TRACEPKT5
TRACEPKT6
R10
T11
TRACEPKT7
PAOUT1A
L12
M11
PAOUT1B
PAOUT2A
K12
J12
PAOUT2B
PIPESTAT0
T9
U9
PIPESTAT1
W8
PIPESTAT2
T13
PM_INT
U14
RESET_N
RF_CLK
B18
RF_DATA
C16
RF_STR0
C17
A17
RF_STR1
RSTOUT_N
F18
RTCK
D18
RTC_OUT
V12
C12
MMCI_DAT0
MMCI_DAT1
D12
B12
MMCI_DAT2
A12
MMCI_DAT3
MON1
B13
A14
MON2
W19
NC1
W14
NC2
NC3
W1
NC4
A19
A1
NC5
NC6
U15
NC7
R11
NC8
L5
NC9
H5
OSC32K
V13
F4
KP_OUT1
C2
KP_OUT2
KP_OUT3
C1
U17
M0
M1
W17
W18
M10
W16
M2
M7
W15
V16
M8
M9
V17
M18
MICN1
MICN2
P19
MICP1
M17
N18
MICP2
C11
MMCI_CLK
MMCI_CMD
E12
H16
I2S2WA1
J18
I2S2_CLK0
H17
I2S2_CLK1
I2S2_RX
H19
I2S2_TX
H18
IRDA_RX
B2
A2
IRDA_TX
M16
IREF
D2
KP_IN0
D1
KP_IN1
KP_IN2
D5
KP_IN3
F5
E3
KP_IN4
E2
KP_IN5
KP_IN6
E1
KP_OUT0
D3
EPPA12
R18
EPPA2
V18
EPREF1
V19
U19
EPREF2
F26M
U12
U13
F32K
G2
FCDP_RB_N
GUARD
K15
I2C_SCL
C3
I2C_SDA
E4
I2S1_CLK0
F19
G16
I2S1_CLK1
G17
I2S1_RX
I2S1_TX
G15
I2S1_WA0
E18
J19
I2S2WA0
T3
EBU_CKE
EBU_CS0_N
P4
V1
EBU_CS1_N
EBU_CS2_N
T2
EBU_CS3_N
P3
EBU_RAS_N
M2
N3
EBU_RD_N
EBU_SDCLK1
U4
U3
EBU_SDCLKO
T6
EBU_WAIT_N
EBU_WR_N
U1
EPN11
P18
N17
EPN12
R19
EPP11
EPP12
T19
T18
EPPA11
EBU_AD14
V7
R7
EBU_AD15
W3
EBU_AD2
EBU_AD3
T5
R6
EBU_AD4
EBU_AD5
U5
W4
EBU_AD6
EBU_AD7
W5
U6
EBU_AD8
V5
EBU_AD9
EBU_ADV_N
T7
EBU_BC0_N
M3
P2
EBU_BC1_N
EBU_BFCLKI
V3
R3
EBU_BFCLKO
M4
EBU_CAS_N
R2
EBU_A22
EBU_A23
U2
EBU_A24
V2
EBU_A3
J2
EBU_A4
J3
K1
EBU_A5
EBU_A6
K2
K3
EBU_A7
EBU_A8
K5
L2
EBU_A9
V4
EBU_AD0
EBU_AD1
R4
EBU_AD10
V6
W6
EBU_AD11
EBU_AD12
T8
U7
EBU_AD13
DSP_OUT1
F2
H2
EBU_A0
EBU_A1
H3
EBU_A10
L1
M1
EBU_A11
EBU_A12
N1
K4
EBU_A13
L4
EBU_A14
EBU_A15
P1
L3
EBU_A16
EBU_A17
R1
N2
EBU_A18
EBU_A19
N4
J4
EBU_A2
N5
EBU_A20
EBU_A21
T1
DIF_D1
C7
DIF_D2
B6
D8
DIF_D3
E7
DIF_D4
DIF_D5
A5
DIF_D6
D7
C6
DIF_D7
B4
DIF_HD
C5
DIF_RD
DIF_RESET1
D6
C4
DIF_RESET2
DIF_VD
B3
DIF_WR
A3
DSP_IN0
F3
G5
DSP_IN1
F1
DSP_OUT0
A11
CIF_D3
CIF_D4
D11
CIF_D5
B10
A10
CIF_D6
B9
CIF_D7
CIF_HSYNC
A8
CIF_PCLK
C9
CIF_PD
B8
CIF_RESET
C8
D10
CIF_VSYNC
E9
CLKOUT
H1
CLKOUT0
B5
DIF_CD
A4
DIF_CS1
DIF_CS2
E6
A6
DIF_D0
C15
AFC
N16
AGND
R13
BB_I
BB_IX
R14
BB_Q
P15
BB_QX
N15
J16
CC_CLK
CC_IO
L18
CC_RST
M19
CIF_D0
E11
CIF_D1
B11
C10
CIF_D2
C109
U102
PMB8876
1u
2V72_IO
R105
NA
C111
0.01u
C108
0.1u
0.1u
C126
C116
1u
R118
R114
10K
100K
CTS
12
DSR
10
GND
1
NC1
4
7
NC2
NC3
8
9
NC4
5
ON_SW
11
RTS
RX
2
3
TX
VBAT
6
2V85_SIM
UART1
220n
C131
R103
4.7
1V5_CORE
VSUPPLY
TP115
1V8_MEM
0.1u
C120
1u
C119
C115
0.1u
C125
0.1u
R126
22K
C104
1V8_MEM
0.1u
22
TP106
R123
C121
C118
0.01u
0.1u
0.01u
C135
R117
0
NA
R446
R445
NA
R109
3.3K
H3
_F3_CE
_F4_CE_A27
E6
D5
_F_ADV
G7
_F_RST
_F_WP1
E1
_F_WP2
F1
_OE
H7
_S_CS1
F6
E2
_WE
R106
22K
VSS2
C3
C4
VSS3
C6
VSS4
VSS5
C7
C8
VSS6
K2
VSS7
VSS8
K3
K4
VSS9
F2
_D1_CS
E3
_D2_CS
F3
_D_CAS
_D_CLK
H5
_D_RAS
F4
H6
_D_WE
_F1_CE
G3
G2
_F2_CE
J1
F_VPP
J9
F_WAIT
D8
N_ALE
E5
N_CLE
N_RY__BY
H1
G1
RFU
H2
S_CS2
S_VCC
D2
VCCQ1
J2
J3
VCCQ2
J7
VCCQ3
J8
VCCQ4
C2
VSS1
K6
VSS10
VSS11
K7
K8
VSS12
H4
D_BA1
G6
D_CKE
J5
D_CLK
D_DM0__S_LB
H9
D_DM1__S_UB
H8
D_LDQS
M3
M7
D_UDQS
D_VCC1
C5
D3
D_VCC2
D7
D_VCC3
F_CLK
K5
B6
F_DPD
F_VCC1
D4
F_VCC2
D6
F_VCC3
J4
F_VCC4
J6
DQ13
K9
L9
DQ14
M8
DQ15
DQ2
K1
DQ3
L2
M4
DQ4
L3
DQ5
L4
DQ6
L5
DQ7
DQ8
M5
DQ9
L6
A1
DU1
A9
DU2
DU3
M1
M9
DU4
D_BA0
G4
A6
A23
A7
A24
A25
A8
B8
A26
B2
A3
A4
A2
B3
A5
A6
A3
A7
A4
G8
A8
F8
A9
M2
DQ0
L1
DQ1
M6
DQ10
L7
DQ11
DQ12
L8
A0
D1
C1
A1
E8
A10
G9
A11
A12
F9
A13
E9
A14
D9
C9
A15
A16
B9
A17
B4
A18
B5
A5
A19
A2
B1
A20
F7
A21
E7
A22
B7
23
24
G1
G2
G3
G4
U101
PF38F5060M0Y0B0
7
8
9
16
25
26
27
28
29
30
17
18
19
20
21
22
1
10
11
12
13
14
15
2
3
4
5
6
CN101
C136
0.1u
0.1u
C134
22
R112
2V72_IO
1V8_MEM
R444
0
3V1_USB
TP130
1V5_CORE
C117
0.1u
2V72_IO
1V8_MEM
TP119
2V85_CARD
2V11_RTC
2V72_IO
R131
NA
R443
0
15p
15p
C133
C132
C107
0.1u
0.1u
C105
1K
R136
0.1u
C127
C129
0.1u
0.1u
0.1u
C130
C128
NA
R104
0.1u
C106
0.1u
C102
0
R101
R102
0
R122
3.3K
1V8_MEM
1V8_MEM
TP116
22
R113
C113
C112
0.1u
1u
R110
100K
1V5_DSP
32.768KHz
X101
1
2
TP101
R108
390K
C122
0.1u
R137
TP117
1V8_MEM
1K
22
R124
2V65_ANA
TP114
C110
0.1u
0.1u
C124
C123
0.1u
1V5_DSP
0.1u
C101
VCXO_EN
JACK_TYPE
VMICN
VMICP
RCV_P
_ADV
_BC0
_BC1
RPWRON
ANT_SW3
HOOK_DETECT
A(14)
A(13)
A(12)
TF_PWR_EN
F_DPD
AU_PWR_EN
JACK_DETECT
TDI
TMS
TCK
RTCK
TDO
_EXTRST
TRIG_IN
TRACEPKT(7)
TRACEPKT(0:7)
MON1
MON2
_FLASH1_CS
FM_INT
AF_PWR_EN
_FM_RESET
FM_BBP_SEL
KP_OUT(4)
REMOTE_INT
MIC_GAIN_SEL
LCD_BACKLIGHT
CHG_LED_CTRL
_RD
BFCLKI
_WP
SDCLKI
_RESET
A(0:24)
D(0:15)
TRACEPKT(4)
TRACEPKT(5)
TRACEPKT(6)
TRACECLK
TRACESYNC
PIPESTAT0
PIPESTAT1
PIPESTAT2
TRACEPKT(0)
TRACEPKT(1)
TRACEPKT(2)
TRACEPKT(3)
TRIG_OUT
_TRST
D(13)
D(14)
D(15)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
CKE
SDCLKO
BFCLKO
F_DPD
_WAIT
_RAM_CS
_CAS
_RAS
_WR
A(21)
A(22)
A(23)
A(24)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
D(0)
D(1)
D(10)
D(11)
D(12)
_BT_RESET
DIF_CD
_USB_EOC
MON1
A(0)
A(1)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(2)
A(20)
CIF_D(3)
CIF_D(2)
CIF_D(1)
CIF_D(0)
USIF_TXD
USIF_RXD
TX_DEBUG
RX_DEBUG
TXD_0
RXD_0
RTS_0
CTS_0
CLK32K
KP_IN(5)
PM_INT
_SIM_EN
SPK_RCV_SEL
CIF_PD
TRIG_OUT
TRACEPKT(0)
TRACEPKT(1)
TRACEPKT(2)
TRACEPKT(3)
TRACEPKT(4)
TRACEPKT(5)
TRACEPKT(6)
TRACEPKT(7)
FLASH_EN
RF_TEMP
DIF_D(0:7)
CIF_D(0:7)
AFC
DSR
TRACEPKT(0:7)
A(0:24)
DIF_D(7)
DIF_D(6)
DIF_D(5)
DIF_D(4)
DIF_D(3)
DIF_D(2)
DIF_D(1)
DIF_D(0)
CIF_D(7)
CIF_D(6)
CIF_D(5)
CIF_D(4)
SDCLKO
BFCLKO
I_MONITOR
CTS_0
RPWRON_EN
RXD_0
RTS_0
DSR
TXD_0
VSUPPLY
D(0:15)
PIPESTAT0
PIPESTAT1
PIPESTAT2
_RESET
RF_CLK
RF_DA
RF_EN
TF_DETECT
RTCK
RTC_OUT
TCK
TDI
TDO
TMS
TRACECLK
TRACESYNC
TRIG_IN
_TRST
TXON_PA
VIBRATOR_EN
PA_BAND
ANT_SW1
ANT_SW2
MODE
USB_DM
USB_DP
VCXO_EN
KP_IN(0)
KP_IN(1)
KP_IN(2)
KP_IN(3)
KP_IN(4)
KP_OUT(5)
KP_OUT(0)
KP_OUT(1)
KP_OUT(2)
KP_OUT(3)
BATT_TEMP
REMOTE_ADC
MIC1_N
MIC2_N
MIC1_P
MIC2_P
TF_CLK
TF_CMD
TF_DAT0
TF_DAT1
TF_DAT2
TF_DAT3
MON2
PA_LEVEL
_ADV
_BC0
_BC1
BFCLKI
_CAS
CKE
_FLASH1_CS
_RAM_CS
_FLASH2_CS
_CS3
_RAS
_RD
SDCLKI
_WAIT
_WR
RCV_N
BBP_SND_L
BBP_SND_R
26MHZ_MCLK
FCDP
SCL
SDA
I2S1_CLK
I2S1_RX
I2S1_TX
I2S1_WA
_WP
A(18)
A(19)
A(2)
A(20)
A(21)
A(22)
A(23)
A(24)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
I
IX
Q
QX
SIM_CLK
SIM_IO
SIM_RST
CIF_HS
CIF_PCLK
CIF_RESET
CIF_VS
CIF_MCLK
DIF_CS
DIF_RESET
DIF_WR
A(0)
A(1)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
7. CIRCUIT DIAGRAM
LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
