6. BLOCK DIAGRAM
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Copyright © 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
OMAP4430
(AP)
XMM6260 (CP)
BT / WiFi
BCM4330
Analog
MIC1
MBIAS
HBIAS
HS_MICN
HSL
HSR
3.5
Φ
HS_MICBIAS
HS_MIC
EAR_L
EAR_R
HOOK_ADC
ACCONN
PDMDN
PDMUP
PDMCLK
PDMCLKLB
PDMFRAME
SDA
SCL
AUDPWRON
NRESPWRON
NAUDINT
PDM_DL_DATA
PDM_UL_DATA
ABE_CLKS
PDM_CLK
PDM_FRAME
I2C1_SDA
I2C1_SCL
AUD_PWRON
SYS_nRESPWRON
SYS_nIRQ2
ABE_PDM_DL_DATA
ABE_PDM_UL_DATA
ABE_CLKS
ABE_PDM_LB_CLK
ABE_PDM_FRAME
HDQ_SIO(GPIO_127)
SYS_NIRQ2
SYS_NRESPWRON
I2C1_SDA
I2C1_SCL
TWL6040
(Audio Codec)
BT_PCM_SYNC
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_CLK
IPC_PCM_DOUT
IPC_PCM_DIN
IPC_PCM_CLK
AUD_FSYNC
AUD_IN
AUD_OUT
AUD_CLK
ABE_McBSP1_CLKX
ABE_McBSP1_DR
ABE_McBSP1_DX
ABE_McBSP1_FSX
ABE_McBSP2_CLKX
ABE_McBSP2_DR
ABE_McBSP2_DX
ABE_McBSP2_FSX
IPC_PCM_SYNC
I2S2_CLK0
I2S2_TX
I2S2_RX
I2S2_WA0
SPEAKER
(1511 FSD 0.5cc Module )
EARP
EARN
HFRP1
HFRN1
AUD_SPK_P
AUD_SPK_N
AUD_RCV_P
AUD_RCV_N
MMICN
MMICP
Analog
MIC2
SMICN
SMICP
EAR_SENSE
PLUGDET
13. Audio Block Diagram_U2 (EU)
RECEIVER
Invisible
(
1207 2.7T WB 30mW)
A
U
D
_C
LK
_I
N
C
LK
32
K
_A
U
D
C
LK3
2K
M
C
LK
VDDIO
VSEL
_1
.8
V
VSEL
_2
.1
V
VBAT
Call
Mp3
Recording
BT Call
Call
Call
HS_MICP
SE
SE
SE
DIFF, 32
옴
SE
SE : Single ended, DIFF : Differential
DIFF, 8
옴
TWL6030
(PMIC)
C
LK3
CDC3S04
(Buffer IC)
CLK32KAUDIO
Short Detect
MBIAS
HS_MIC_GND
AFMR
AFML
SE
FM_AOUT1
FM_AOUT2
FM_ANT
FM
Tunning
Circuit
BT
PlayBack
BT_UART_TXD
BT_UART_RXD
BT_UART_CTS/
BT_UART_RTS
BT_UART_RXD
BT_UART_TXD
BT_UART_RTS_N
BT_UART_CTS_N
UART2_CTS/
UART2_RTS/
UART2_RX
UART2_TX
Audio Block Diagram__P768