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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
2.2u
L2300
FL2300
4.3u
IN
OUT
GND1 GND2
FL2301
4.3u
IN
OUT
GND1 GND2
FL2302
4.3u
IN
OUT
GND1 GND2
FL2303
4.3u
IN
OUT
GND1 GND2
FL2304
4.3u
IN
OUT
GND1 GND2
FL2305
4.3u
IN
OUT
GND1 GND2
1u
C2398
1u
C2399
FL2306
4.3u
IN
OUT
GND1 GND2
FL2307
4.3u
IN
OUT
GND1 GND2
FL2308
4.3u
IN
OUT
GND1 GND2
FL2309
4.3u
IN
OUT
GND1 GND2
C2400
1u
+1V0_VREG_L11
R2300
0
C2335
1u
R2313
0
U2100
MSM8974AC
E2
1
T4
J5
F6
L7
K
4
P4
F2
R3
J1
BD36
BC41
BC21
AW11
AV4
2
AU11
AL35
AL33
AL31
AL13
AL11
AH44
AG33
AG31
AG29
AG27
AG25
AG23
AG13
AG11
AE2
7
AC21
AC19
AC13
AC11
AB4
4
W4
1
W3
9
W3
5
W3
3
W2
3
W1
7
W1
5
R35
R25
R23
R21
R15
R13
R11
L33
L31
L15
L13
L11
K44
H18
H16
H12
BF26
BE3
9
BE3
3
BD28
BD26
BF28
BD38
BC37
AB48
AD48
AW39
AW37
AW35
AW33
AW31
AR41
AR39
AR33
AR31
AL41
AL39
AG41
AG39
AG37
BA41
BA39
BA37
BA35
BA13
AW21
AW13
AU37
AU17
AR37
AR35
AR21
AN37
AN15
AL37
AL29
AL27
AL21
AL19
AG35
AC17
AC15
AA31
W31
W21
W19
W13
W11
R33
R31
R19
R17
L35
L19
L17
H34
AC41
AC39
AC37
AC29
AC27
AC25
U41
U39
U37
U29
U27
U25
N41
N39
N37
N29
N27
N25
J41
J39
J37
J29
J27
J25
BD14
BC11
AN43
AH8
J9
BB44
T44
G37
F30
F14
BF10
BC19
AR43
AM8
L9
BF38
W43
F42
D8
B30
AH48
AF48
AC47
C15
BG21
BC39
BC15
AY44
AK8
AH46
P48
N5
G45
G39
G31
G23
G9
E19
T46
BK32
BJ47
BJ45
BJ35
BJ17
BJ5
BF40
BE15
BD48
BD10
BA1
AV44
AN47
AJ49
AH2
AG7
U49
T2
P44
L3
K8
J49
G41
G27
G11
E1
B38
B16
B6
F3
6
BD
8
AY8
AW
7
AT
2
AK
4
AH
4
AB8
AE4
5
AC31
AA2
3
J2
3
G4
3
AW29
H20
AU29
AR29
AG15
AF46
AE4
3
AE3
5
N23
AP4
8
U47
R45
BG
3
BF
4
BD
2
BB4
BB2
0
BB1
8
AW25
AW23
AW19
AW17
AW15
AR25
AR23
AR19
AR17
AR15
AL25
AL23
AL17
AL15
AG21
AG19
AG17
BJ2
5
BF
2
AD50
D50
D2
BK
4
BH48
BG25
AV2
AE4
9
AD
2
E4
9
C37
B2
6
B4
VDD_DDR_CORE_1P2_0
1
VDD_DDR_CORE_1P2_0
2
VDD_DDR_CORE_1P2_0
3
VDD_DDR_CORE_1P2_0
4
VDD_DDR_CORE_1P2_0
5
VDD_DDR_CORE_1P2_0
6
VDD_DDR_CORE_1P2_0
7
VDD_DDR_CORE_1P2_0
8
VDD_DDR_CORE_1P2_0
9
VDD_DDR_CORE_1P2_1
0
VDD_DDR_CORE_1P8_0
1
VDD_DDR_CORE_1P8_0
2
VDD_DDR_CORE_1P8_0
3
VDD_DDR_CORE_1P8_0
4
VDD_DDR_CORE_1P8_0
5
VDD_GFX_01 VDD_GFX_02 VDD_GFX_03 VDD_GFX_04 VDD_GFX_05 VDD_GFX_06 VDD_GFX_07 VDD_GFX_08 VDD_GFX_09 VDD_GFX_10 VDD_GFX_1
1
VDD_GFX_12 VDD_GFX_13 VDD_GFX_14 VDD_GFX_15 VDD_GFX_16 VDD_GFX_17 VDD_GFX_18 VDD_GFX_19
VDD_MIPI_DSI_0P4
MIPI_DSI_LD
O
VDD_MIPI_DSI_1P
2
VDD_MIPI_DSI_1P8
VREF_SD
C
VDD_SDC_CDC_01 VDD_SDC_CDC_02
VDD_PLL1_0
1
VDD_PLL1_0
2
VDD_PLL1_0
3
VDD_PLL1_0
4
VDD_PLL1_0
5
VDD_PLL1_0
6
VDD_PLL1_0
7
VDD_PLL2_0
2
VDD_PLL2_0
9
VDD_PLL2_0
1
VDD_PLL2_0
3
VDD_PLL2_0
4
VDD_PLL2_0
5
VDD_PLL2_0
6
VDD_MIPI_CS
I
VDD_PLL2_0
7
VDD_HDM
I
VDD_PLL2_0
8
VDD_EDP
VDD_PLL2_1
0
VDD_PLL2_1
1
VDD_QFPROM_PR
G
VDD_P1_01
VDD_P1_02
VDD_P1_03
VDD_P1_04
VDD_P1_05
VDD_P1_06
VDD_P1_07
VDD_P1_08
VDD_P1_09
VDD_P1_10
VDD_P1_11
VDD_P1_12
VDD_P1_13
VDD_P1_14
VDD_P1_15
VDD_P1_16
VDD_P1_17
VDD_P1_18
VDD_P1_19
VDD_P1_20
VDD_P1_21
VDD_P1_22
VDD_P1_23
VDD_P1_24
VDD_P1_25
VDD_P1_26
VDD_P1_27
VDD_P1_28
VDD_P1_29
VDD_P2
VDD_P3_01
VDD_P3_02
VDD_P3_03
VDD_P3_04
VDD_P3_05
VDD_P3_06
VDD_P3_07
VDD_P3_08
VDD_P3_09
VDD_P3_10
VDD_P3_11
VDD_P3_12
VDD_P3_13
VDD_P3_14
VDD_P4
VDD_P5
VDD_P6
VDD_P7
VDD_EBI0_CDC_01
VDD_EBI0_CDC_02
VDD_EBI0_CDC_03
VDD_EBI0_CDC_04
VDD_EBI0_CDC_05
VDD_EBI1_CDC_01
VDD_EBI1_CDC_02
VDD_EBI1_CDC_03
VDD_EBI1_CDC_04
VDD_EBI1_CDC_05
VDD_EBI0_PLL_01
VDD_EBI0_PLL_02
VDD_EBI0_PLL_03
VDD_EBI0_PLL_04
VDD_EBI0_PLL_05
VDD_EBI1_PLL_01
VDD_EBI1_PLL_02
VDD_EBI1_PLL_03
VDD_EBI1_PLL_04
VDD_EBI1_PLL_05
VDD_KRAIT_01
VDD_KRAIT_02
VDD_KRAIT_03
VDD_KRAIT_04
VDD_KRAIT_05
VDD_KRAIT_06
VDD_KRAIT_07
VDD_KRAIT_08
VDD_KRAIT_09
VDD_KRAIT_10
VDD_KRAIT_11
VDD_KRAIT_12
VDD_KRAIT_13
VDD_KRAIT_14
VDD_KRAIT_15
VDD_KRAIT_16
VDD_KRAIT_17
VDD_KRAIT_18
VDD_KRAIT_19
VDD_KRAIT_20
VDD_KRAIT_21
VDD_KRAIT_22
VDD_KRAIT_23
VDD_KRAIT_24
VDD_MEM_01
VDD_MEM_02
VDD_MEM_03
VDD_MEM_04
VDD_MEM_05
VDD_MEM_06
VDD_MEM_07
VDD_MEM_08
VDD_MEM_09
VDD_MEM_10
VDD_MEM_11
VDD_MEM_12
VDD_MEM_13
VDD_MEM_14
VDD_MEM_15
VDD_MEM_16
VDD_MEM_17
VDD_MEM_18
VDD_MEM_19
VDD_MEM_20
VDD_MEM_21
VDD_MEM_22
VDD_MEM_23
VDD_MEM_24
VDD_MEM_25
VDD_MEM_26
VDD_MEM_27
VDD_MEM_28
VDD_MEM_29
VDD_MEM_30
VDD_MEM_31
VDD_MEM_32
VDD_MEM_33
VDD_MEM_34
VDD_MEM_35
VDD_MEM_36
VDD_MODEM_01
VDD_MODEM_02
VDD_MODEM_03
VDD_MODEM_04
VDD_MODEM_05
VDD_MODEM_06
VDD_MODEM_07
VDD_MODEM_08
VDD_MODEM_09
VDD_MODEM_10
VDD_MODEM_11
VDD_MODEM_12
VDD_MODEM_13
VDD_MODEM_14
VDD_ALWAYS_ON
VREF_UIM
VDD_A1_01 VDD_A1_02 VDD_A1_03
VDD_A2_0
1
VDD_MEM_37
VDD_A2_0
3
VDD_A2_04 VDD_A2_05
VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_1
7
VDD_CORE_1
8
VDD_CORE_1
9
VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28 VDD_CORE_29 VDD_CORE_30 VDD_CORE_31 VDD_CORE_32 VDD_CORE_33 VDD_CORE_34 VDD_CORE_35 VDD_CORE_36 VDD_CORE_37 VDD_CORE_38 VDD_CORE_39 VDD_CORE_40 VDD_CORE_41 VDD_CORE_42 VDD_CORE_43 VDD_CORE_44 VDD_CORE_45 VDD_CORE_46 VDD_CORE_47 VDD_CORE_48 VDD_CORE_49
VDD_USB_3P3_01 VDD_USB_3P3_02
VDD_USB_1P8_01 VDD_USB_1P8_03 VDD_USB_1P8_02
USB_SS_VPTX
VDD_USB_CORE_0
2
VDD_USB_CORE_0
3
VDD_USB_CORE_0
1
VDD_WLA
N
C2303
47u
C2300
1u
C2320
1u
C2392
47u
47u
C2391
C2316
1u
+1V3_VREG_L4
C2313
1u
DNI
C2395
DNI
C2393
C2348 1u
+0V9_VREG_S2B
C2317
1u
1u
C2301
C2302
1u
+1V8_VREG_L6
+3V075_VREG_L24
+0V9_VREG_S2B
R2309
0
C2312
1u
2.2u
C2371
1u
C2308
C2310
1u
1u
C2309
1u
C2305
1u
C2318
C2307
1u
1u
C2306
+0V9_VREG_S2B
+1V8_VREG_L14
1u
C2314
+1V3_VREG_L4
1u
C2319
22u
C2334
22u
C2333
C2332
22u
22u
C2331
+0V9_VSENSE_KRAIT
+0V9_VREG_KRAIT
C2315
1u
+0V95_VREG_S1B
+0V95_VREG_S1B_ISO
+1V15_VREG_S3B
C2360
0.1u
SDC_UIM_VREF
TP2300
1u
C2372
+1V8_VREG_L12
+1V8_VREG_L12
1u
C2385
C2384
1u
1u
C2388
C2386
1u
C2387
1u
1u
C2389
+1V8_VREG_L12
C2375
1u
+1V8_VREG_L12
1u
C2374
C2379
1u
1u
C2378
C2377
1u
1u
C2376
C2373
0.1u
SDC_UIM_VREF
+1V8_VREG_L12
1u
C2390
+1V2_VREG_L2
C2311
1u
+0V9_VREG_S4B
1u
C2382
1u
C2381
1u
C2380
1u
C2383
+1V8_VREG_S3A
1u
C2362
C2369
1u
1u
C2368
1u
C2367
1u
C2365
C2364
1u
1u
C2363
1u
C2366
C2370
1u
C2361
1u
+1V2_VREG_L1
+0V95_VREG_S1B
+0V95_VREG_S1B_ISO
1u
C2359
C2355
1u
C2352
1u
1u
C2353
1u
C2354
1u
C2356 C2357
1u
C2358
1u
1u
C2351
C2350
1u
C2349
1u
+1V8_VREG_S3A
+1V8_VREG_S3A
UIM1_VREG_L9
+1V8_VREG_S3A
C2336
1u
C2337
1u
C2338
1u
C2339
1u
C2346
1u
C2345
1u
1u
C2344
C2342
1u
C2341
1u
C2340
1u
1u
C2343
1u
C2347
+1V8_VREG_S3A
+2V95_VREG_L13
C2321
1u
C2322
1u
1u
C2330
C2329
1u
1u
C2328
1u
C2327
C2326
1u
1u
C2325
C2324
1u
C2323
1u
+1V2_VREG_L1
47u
C2304
REMOTE_GND_SNS
REMOTE_GND_SNS|GND
+0V9_VSENSE0V9_VREG_KRAIT
rev10
12/26
01/23
12/30
1/23
NOTE 2:QMC Checklist Rev.C
pin group: (BD38, BC37), BF28
10/11
10/11
0 ohm --> Net Short
AW7 PIN assign need to check !
10/14
rev10
DNI cap. for PDN
DNI cap.for PDN
12/20
1 ¡¿ 1 ¥ìF cap each close to the following pin or
NOTE 7:QMC Checklist Rev.C
3 ¡¿ 1 ¥ìF cap, one cap each close to pin F2, P4, K4
OUTPUT CAPACITORS CLOSE TO MSM
NOTE 10:QMC Reference Schematic Rev.K
(AP48, AE43, AF46), U47, (AR29, AU29)
share one 1 ¥ìF cap): (AE35, AG15 ,N23),
pin group (pins in a bracket is a group and
1 ¡¿ 1 ¥ìF cap each close to the following pin or
NOTE 5:QMC Checklist Rev.K
NOTE 9:QMC Checklist Rev.K
NOTE 8:QMC Reference Schematic Rev.L
NOTE 4:QMC Checklist Rev.C
NOTE 3:QMC Chekclist Rev.C
NOTE 1:QMC Reference Schematic Rev.L
Based on Reference Schematic
Release Date
need to be routed differentially
VSENSE_KRAIT_0P9 and REMOTE_GND_SNS
VSENSE_KRAIT_0P9, REMOTE_GND_SNS
NOTE 6:QMC Checklist Rev.K
VDD_PLL1 pins directly to the main VDD_CORE plane.
VDD_CORE plane. Do not short the VDD_SDC_CDC,
and pins VDD_SDC_CDC, VDD_PLL1 star route to the
Place a 0 ¥Ø series resistor between VREG_S2B_0P9
VREG_S1B_0P95
net back to the main plane at the location of the resistor.
customer can remove the resistor and simply short the isolated
stage to achive the desired isolation. Once routing is complete
We recommend to keep the resistors in the design during the routing
and does not allow shorting to the plane.
The resistor forces a separate netname and a separate routing
to VDD_MX rather than just short to a plane.
the VDD_EBI_CDC and VDD_EBI_PLL pins are to star connects
Place a 0 ¥Ø resistors between VREG_S1B_0P95 and
OUTPUT CAPACITORS CLOSE TO MSM
PLACE S2B, S4B, S5B, S6B, S7B, S8B
OUTPUT CAPACITORS CLOSE TO MSM
PLACE S2B, S4B, S5B, S6B, S7B, S8B
VREG_S2B_0P9
If GPIO144/145 is used, connect VDD_P4 to 1.80 V(VREG_S3A_1P8)
If HSIC is used, connect VDD_P4 to 1.2 V (VREG_L1_1P2)
CCDS CARD Information
Rev_0.1
2013.08.26
PLACE S2B, S4B, S5B, S6B, S7B, S8B
Rev.M
80-NA437-41_MSM8974-MSM8974AB_BASEBAND_REFERENCE_SCHEMATIC Rev.M
<2-1-2-2-3_MSM8974AB_POWER>
10/11
10/11
10/14
12/20
10/14
10/14
rev.B
REV10
REV10
REV10