2-12
2. IC302 (BA00CCOWFP)
2-1. BLOCK DIAGRAM
2-2. PIN NO., PIN NAME
3. IC401 (µPD78F1164)
3-1. PIN CONFIGURATION
PE
X
L
VI
(I)
PFL
MD0_
CT
R(O)
P
RDS_
C
L
K(
I)
PF
RT_DO(O)
PF
RT_DI(
I)
PF
RT_CLK
(O)
PA
N
T
(O
)
DOWNLOAD_CLK
DOWNLOAD_IO
RES
E
T
SUB_
CLK
(32.768K
hz)
SUB_
CLK
(32.768K
hz)
FL
M
D
0
X’T
AL(19.2,Mhz)
X;T
AL(19.2Mhz)
REGC
Vs
s
EV
ss
Vd
d
EVdd
AV
re
f0
PT
U
N
E
R
_M
U
TE(
O)
PL
IN
E_MUTE(O)
AV
re
f
PP
LL_CLK
(I
)
PP
LL_DI(I)
PP
LL_DO(O)
PU
SB_TX/P
BT_TX(O)
PU
S
B
_R
X
/PB
T
_R
X
(I
)
PV
OLB(I)
PV
O
L
A
(I
)
P
ACC
_O
U
T
(O
)
P
ACC
_IN
(I
)
PO
PT
_O
U
T
2(
O
)
PO
PT
_O
U
T
1(
O
)
PO
PT
_O
U
T
0(
O
)
PO
PT
_I
N
2(
I)
PO
PT
_I
N
1(
I)
PO
PT
_I
N
0(
I)
PU
S
B
_PROTECT(I)
PBEEP(O)
PFRT_CE(I)
PCDP_CLK(O)
PCDP_DI(I)
PCDP_DO(O)
PFRT_RST(O)
PFRT_OPEN(I)
PFRT_DETECT(I)
PART_TX(O)
PART_RX(I)
PART_EN(I)
PSD_ST(I)
PPLL_CE(O)
PEEPROM_CE(O)
PDIM_IN(I)
PRDS_DI(I)
PPWR(O)
PREMOTE(O)
PTEL_MUTE(I)
PAUDIO_MUTE(O)
PAUX_MUTE(O)
PLIGHT(O)
PDIM_OUT(O)
PEJECT(I)
PQUALTY(I)
PSMETER(I)
PLEVEL_METER(I)
PKEY2(I)
PKEY1(I)
AVss
PEV_CLK(O)
PEV_CE(O)
PPWR_MUTE(O)
PAF_MUTE(O)
PRMC(I)
PSOFT_MUTE(O)
PEALA_SW1(O)
PEALA_SW2(O)
PSPEC_CLK(O)
PSTANDBY(O)
PDECK_LD(I)
PCDP_BLK(I)
PCDP_VDET(I)
PCDP_POWER(O)
PDECK_INN(I)
PDECK_12/8(I)
PSLED_CTRL(O)
PRCP_FEW(O)
PCDP_REW(O)
EVss1
PDRV_MUTE(O)
PDAC_MUTE(O)
PCDP_RST(O)
PCDP_MLD(O)
PZERO_MUTE(I)
PISP(O)
PUSB_POWER/PBT_POWER(O)
PUSB_SW(I)
PUSB_RESET(O)
EVdd1
uPD78F1164
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only