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Copyright
2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
BLOCK DIAGRAM
L
V D S
Analog 1(R/G/B)
D-Sub 1
LIPS
Filter
5V
15V
5V
Regulator
3.3V
Vcc
5V
Inverter(4Lamps)
15
V
Flash ROM
DVI-D
DVI(TMDS)
KEY
1.8V
1.8V
3.3V
Module
SDA
/SCL
EEPROM
(EDID)
EEPROM
(System)
3.3
EEPROM
(EDID)
Crystal
14.318MHz
Crystal Location No : X501
135Mhz
Dual
Interface
Engine
Display
Processing
Engine
Response
T
ime
Enhancement
L
VDS
Panel
Interface
OSD
Clock
Generator
MCU
DRAM
TSUMO56WHJ-LF
3.3V
5V