
37
SCHEMATIC DIAGRAM
B3
3.INPUT
RIN
GIN
BIN
VSYNC
GNDR
GNDG
GNDB
DET_VGA
HSY NC
SOG
DDCA_SDA
DDCA_SCL
+5V
DDC_WP
PC5V
VCC3.3
PC5V
A[0..9]
VLCD
XGA/SXGA
+5V
TSUM16AL SCHEMATIC
B5
5.PANEL INTERFACE
VLCD
B[0..9]
A[0..9]
VLCD
+5V
B4
4.SCALER
RIN
GIN
SOG
BIN
GNDR
GNDG
GNDB
HSY NC
VSYNC
Adj_BACKLIGHT
VCC1.8
Vcc3.3
VCTRL
A[0..9]
B[0..9]
DDCA_SDA
DDCA_SCL
DET_VGA
on_BACKLIGHT
on_Panel
+5V
DDC_WP
VCC1.8
VCC1.8
B[0..0]
PC5V
B2
2.POW ER
on_Panel
on_BACKLIGHT
Adj_BACKLIGHT
VCC1.8
VLCD
+5V
VCTRL
VCC5V
VCC3.3
PC5V
LVDS OUTPUT
VCC3.3
+5V
VCC5V
1. SCALER