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3. TECHNICAL BRIEF
SMARTiPM features a direct conversion receiver and a quad-band polar modulator transmitter forGSM
and EDGE. An analog I/Q baseband interface is provided. The HSCSD and GPRS/EDGE capable
synthesizer is fully integrated, including all RF oscillators. A reference oscillator buffer amplifier with
three outputs is provided to simplify clock distribution. A three wire bus interface is used for control and
programming. SMARTi3G is a triple-band W-CDMA transceiver for voice and high speed data
applications. SMARTi3G features a direct conversion receiver and a direct modulation transmitter.
Analog I/Q baseband interfaces are supported. A three wire bus interface is provided for control and
programming. A second three wire bus may optionally be used for fast control of the receiver
programmable gain amplifier. Fractional-N PLL RF synthesizers including separate TX and RX VCOs
are fully integrated. Programmable logic outputs are provided to control external low noise amplifiers,
power amplifiers, and antenna switches. To avoid interference between the 2.5G and 3G transceivers,
simultaneous operation of SMARTiPM and SMARTi3G is not permitted.
LGE Internal Use Only
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
TXOUTH/TXOUTHX
1920-1980 MHz
(band I)
RXINH/RXINHX
2110-2170 MHz (band I)
RXINM/RXINMX
1930-1990 MHz (band II/III)
TXOUTL/TXOUTLX
824-849 (band V/VI)
TXOUTM/TXOUTMX
1850-1910 MHz
(band II/III)
RXINL/RXINLX
869-894 (band V/VI)
RXBAND1
RXBAND2
RXBAND3
EN / DATA / CLK
FSYSIN_3G
RXQ/RXQX
RXI/RXIX
ENPGC
DATAPGC
CLKPGC
TXI/TXIX
TXQ/TXQX
TXGC
MASTERON
LD
TXHSMODE
TXEN
TXBAND1
TXBAND2
TXBAND3
1.71...2.95V Supply
:2
0
o
90
o
VCO
Frac-PLL
LF
:4
0
o
90
o
I
Q
0
o
90
o
VCO
Frac-PLL
LF
0
o
90
o
Internal
1.5V
LDO
TX gain
control
3-wire bus
RX PGC
FSYS
SMARTi 3G
:4
:2
3-wire bus
:2
0
o
90
o
2.7...2.95V Supply
1.5V Supply
I/IX
Q/QX
FSYSIN_P M
RX1/RX1X 850MHz
RX2/RX2X 900MHz
RX3/RX3X 1800MHz
RX4/RX4X 1900MHz
TX1 850/900MHz
TX2 1800/1900MHz
VBIAS
FSYSOUT1
EN_PM
DATA_PM
CLK_PM
FSYSOUT2
FSYSOUT3
VCO_RC
2.7...2.95V Supply
1.4...1.6V Supply
fast
PFD
Integrated
3.8GHz V CO
Sigma-Delta
MASH Modulator
multi modulus divider
26 M Hz
VCO
control
fast
CP
3W bus
sequencing
NI.NF
MOD
4
2
OLG
adjust
Timing
&
Measure
ment
on chip
loop filter
cordic
I/Q
=>
R/
d/dt
Q
4
2
V CO-LDO
Bias DAC
2
2
2
2
PGA
6dB
PGA
1dB
.125dB
Ramp
SMARTi PM
DAC
Dig
PGA
I
ADC
ADC
Bias
[Figure 3.16-2] RF Functional Block Diagram