LG KP220 - Cell Phone 60 MB, Service Manual

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5-2-
Tw
1
ith O LL to form a complete transmitter circuit.
he TX ypically 9 dB th +/- 2.5dB variation in E-GSM900/
SM8 utput power
CS19 me temperature conditions. Inside the chip, the VCO
ifferen re fed into the output buffer, the OPLL input feedback
uffer, and the calibration circuit. The off chip signal is transformed into a single
nded output which needs impedance matching to 50_to drive the power amplifier.
ike RF VCO, the oscillation bandwidth is partitioned into 128 (or 64) sub-bands for
CS/ PCS (for E-GSM900/ GSM850) TX VCO to cover the process and temperature
ariation. Calibration process begins after a period of programmable time when the
n chip TX VCO regulator is turned on. Total calibration time needs about 60us
aximally and the frequency error after calibration is /-5 MHz. For Vtune =
.2 V, the variation of kvco is about 14% and 40% for GSM and DCS/PCS TX VCO,
espectively, across the desired fre
5-2-19.4 Frequency Synthesizer
The MT6129 includes a integrated RF VCO to
generate RX and TX local oscillator frequencies. The PLL locks the RF VCO to a
precision reference frequen
the inherent spur
aused by fractional-N syn modulator with
ithering function is used to generate the presale divider number N. The presale is
ased on a multi-modulus architecture with programmable divider numbers ranging
om 64 to 127. A conventional digital-type PFD with a charge pump is used for
hase comparison in the PLL. By changing the output current of the charge pump,
e phase detector gain can be programmed from75/_ _A/rad to 600/_ _A/rad.
fast settling time for multi-slot data
RS, a digital loop (calibration loop) along with a fast-acquisition
d in the synthesizer. Once the synthesizer is programmed,
o the vicinity of the desired frequency by a digital calibration
ation, a fast-acquisition system is utilized for a period of time to
cilitate fast locking. Once the acquisition is done, the PLL reverts back to the
ormal operation mode.
9.3 TX VCO
o power VCOs are integrated w P
T VCO output power is t
m o
m wi
with +/- 2dB variation in DCS1800/ G
P 50 bands and +8 dB
00 bands over extre
tial output signals a
s
d
b
e
L
D
v
o
m
1
r
quency range.
frequency synthesizer with a fully
cy at 26 MHz. In order to reduce
thesizers, a 3rd-order sigma-delta c
d
b
fr
p
th
To reduce the acquisition time or to enable
services such as GP
system are implemente
et t the RF VCO is pre-s
loop. After the calibr
fa
n
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