LG KG920, Service Manual

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3. TECHNICAL BRIEF
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OVERVIEW
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O (L30) device provides read-while-write
and read-while-erase capability with package-compatible density upgrades through 256-Mbit.
This family of devices provides high performance at low voltage on a 16-bit data bus.
Individually erasable memory blocks are sized for optimum code and data storage.
Each device density contains one parameter partition and several main partitions.
The flash memory array is grouped into multiple 8-Mbit main partitions. By dividing the flash memory into
partitions, program or erase operations can take place at the same time as read operations.
Although each partition has write, erase and burst read capabilities, simultaneous operation is limited to
write or erase in one partition while other partitions are in read mode. The L30 flash memory device
allows burst reads that cross partition boundaries.
User application code is responsible for ensuring that burst reads don”t cross into a partition that is
programming or erasing.
Upon initial power up or return from reset, the device defaults to asynchronous pagemode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads.
In synchronous burst mode, output data is synchronized with a user-supplied clock signal.
A WAIT signal provides easy CPU-to-flash memory synchronization.
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes Upper address
inputs to determine the accessed partition. ADV#-low opens the internal address latches.
OE#-low activates the outputs and gates selected data onto the I/O bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if
ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV#
edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL).
Read operation
To perform a read operation, RST# and WE# must be deserted while CE# and OE# are asserted.
CE# is the device-select control. When asserted, it enables the flash memory device.
OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O
bus.