72
Pin no. Pin name
I/O
I/O Setting
Symbol
Description
79
P120
I/O
O
STNBYONP
OEIC power-saving control
80
PX7
I/O
O
(CLKOUT)
For Bus evaluation
81
PX6
I/O
O
Blank port
82
PX5
I/O
O
Blank port
83
Vss
O
VSS
GND
84
P97
I/O
O
EEPRCE
EEPROM Chip Select
85
P96
I/O
O
Blank port
86
P95
I/O
O
DSLADJ2
DSL Adjustment/EQ Boost Filter change single
87
P94
I/O
O
(XBCYST)
For Bus evaluation
88
P93
I/O
O
DSLADJ
Encoder output Loop Back Mute signal
89
P92
I/O
O
XRD
Read Strobe
90
P91
I/O
O
Blank port
91
P90
I/O
O
XLWR
Lower Byte Write Strobe
92
P87
I/O
O
XCS7
DSP3 Chip Select(1Wait)
93
P86
I/O
O
XCS6
DSP3 Chip Select(2Wait)
94
P85
I/O
O
Blank port
95
P84
I/O
O
Blank port
96
P83
I/O
O
LEDG1
LED
97
P82
I/O
O
XCS2
SRAM Chip Select
98
P81
I/O
O
XCS1
FROM Chip Select(Main Part)
99
P80
I/O
O
XCS0
FROM Chip Select(Core Part)
100
HVdd
I
VDD
+3.3V
101
P67
I/O
O
Blank port
102
P66
I/O
O
Blank port
103
P65
I/O
O
Blank port
104
P64
I/O
O
A20
Address Bus 20
105
P63
I/O
O
A19
Address Bus 19
106
P62
I/O
O
A18
Address Bus 18
107
P61
I/O
O
A17
Address Bus 17
108
P60
I/O
O
A16
Address Bus 16
109
PB7
I/O
O
A15
Address Bus 15
110
PB6
I/O
O
A14
Address Bus 15
111
PB5
I/O
O
A13
Address Bus 13
112
PB4
I/O
O
A12
Address Bus 12
113
PB3
I/O
O
A11
Address Bus 11
114
PB2
I/O
O
A10
Address Bus 10
115
PB1
I/O
O
A9
Address Bus 9
116
PB0
I/O
O
A8
Address Bus 8
117
Vss
O
VSS
GND
118
PA7
I/O
O
A7
Address Bus 7
119
PA6
I/O
O
A6
Address Bus 6
120
PA5
I/O
O
A5
Address Bus 5