3-3
IC503
SDRAM
IC701
Front
U-com
X501
/M-RESET
MCLK
IC202
RF IC
R548
IC501
MPEG
(ZIVA5.0)
1) MPEG IC start oscilating(13.5Mhz)after being
installed VCC
2) MPEG IC and RF IC get the /M - RESET signal
from front U - com(IC701) and they are initial-
ized.
3) And then, MPEG IC generate MCLK and send
to SDRAM
4) MPEG IC and SDRAM are synchronized by
MCLK, they communicate between.
If oscilation(13.5Mhz) don’t appear, check
The X-TAL and VCC and replace MPEG IC.
If MCLK don’t appear, first cut the MCLK line
(remove R548) and recheck.
Don’t appear -> check MPEG IC or replace
Appear -> check the SDRAM or replace
/M-RESET X501
Reset Time
Power
Cord in
X501
(13.5 Mhz)
MCLK
(135 Mhz)
IC504
Flash
ROM
IC701
Front
U-com
X501
(13.5Mhz)
/M-RESET
R/W
VCC
data
address
IC501
MPEG
(ZIVA5.0)
1) MPEG IC start oscilating(13.5Mhz) after being
installed VCC
2) MPEG IC is initialized by /M - RESE T
3) MPEG IC send the R/W(read/write) signal
before communicating with FLASH ROM
R/W signal should be confirmed by Flash or the
next step will not continue.
As that result, the initial step(power cord in ->
green LED -> red LED -> standby) will fail.
If R/W signal doesn’t appear, check the VCC and
replace the Flash ROM…
VCC
Power
Cord in
/M-RESET
R/W
3. Initializing between MPEG and SDRAM
4. Initializing between MPEG and Flash