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Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
The AD6548 provides a highly integrated direct conversion radio solution that combines, on a single chip,
all radio and power management functions necessary to build the most com-pact GSM radio solution
possible. The only external components required for a complete radio design are the Rx SAWs, PA,
Switchplexer and a few passives enabling an extremely small cost effective GSM Radio solution. The
AD6548 uses the industry proven direct conversion receiver architecture of the OthelloTM family. For Quad
band applications the front end features four fully integrated programmable gain differential LNAs. The RF
is then down converted by quad-rature mixers and then fed to the baseband programmable-gain
amplifiers and active filters for channel selection. The Receiver output pins can be directly connected to the
baseband analog processor. The Receive path features automatic calibration and tracking to remove DC
offsets. The transmitter features a translation-loop architecture for directly modulating baseband signals
onto the integrated TX VCO. The translation-loop modulator and TX VCO are extremely low noise removing
the need for external SAW filters prior to the PA. The AD6548 uses a single integrated LO VCO for both the
receive and the transmit circuits. The synthesizer lock times are optimized for GPRS applications up to and
including class 12.
AD6548 incorporates a complete reference crystal calibration system. This allows the external VCTCXO to
be replaced with a low cost crystal. No other external components are required. The AD6548 uses the
traditional VCTCXO reference source. The AD6548 also contains on-chip low dropout voltage regulators
(LDOs) to deliver regulated supply voltages to the functions on chip, with a battery input voltage of
between 2.9V and 5.5V. Comprehensive power down options are included to minimize power
consumption in normal use. A standard 3 wire serial interface is used to program the IC. The interface
features low-voltage digital interface buffers compatible with logic levels from 1.6V to 2.9V.
3.2 Transceiver (AD6548, U501)
A
n
te
nna Swi
tch
Mod
u
le
DC Offset
Correction
DC Offset
Correction
PFD
/2
LDO
Reg 3
LDO
Reg 2
LDO
Reg 1
Frac-N Synth
RX LO
Generator
TX LO
Generator
Xtal Osc
+ Tuning
Serial
Interface
/4
SEN
SCLK
SDATA
RX1900B
RX1900
RX1800B
RX1800
RX900B
RX900
RX850B
RX850
TXOP_HI
TXOP_LO
VDD
VBAT
VLDO3
VLDO2
VLDO1
LO VCO
Supply
REF_OP
REFIN
REFINB
VAFC
VCC_REF
Q
QB
I
IB
VCC_BBI
VCC_BBQ
LNA Gain
Reduction
TX_LO2
TX_LO1
TX_LO2
TX_LO1
General
Supply
TX circuits
supply
CLK
RXQB
RXQ
TXQB
TXQ
RXIB
RXI
TXI
TXIB
AFC
REF_OP
Band
Control
TX Loop
Filter
GSM1800/1900
GSM850/900
PA Module
AD6548
VCC_FE
VCC_TXVCO
Ref
Supply
VCC_
TXVCO
Figure 3.3 AD6548 Block Diagram
