LG Flatron L2010P, Service Manual

Page: 34 / 44

- 34 -
THC63LVDM83R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RS
TD1
TA 5
TA 6
GND
TB0
TB1
TD2
VCC
TD3
TB2
TB3
GND
TB4
TB5
TD4
R/F
TD5
TB6
TC0
GND
TC1
TC2
TC3
TD6
VCC
TC4
TC5
TA 4
TA 3
TA 2
GND
TA 1
TA 0
TD0
LVDS GND
TA -
TA +
TB-
TB+
LV DS VCC
LVDS GND
TC-
TC+
TCLK-
TCLK+
TD-
TD+
LVDS GND
PLL GND
PLL VC C
PLL GND
/PDWN
CLK I N
TC6
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RS
TA 5
TA 6
GND
TB0
TB1
VCC
TB2
TB3
GND
TB4
TB5
R/F
TB6
TC0
GND
TC1
TC2
TC3
VCC
TC4
TC5
TA 4 TA3
TA 2
GND
TA 1
TA 0
LV DS GND
TA -
TA +
TB-
TB+
LV DS VCC
LV DS GND
TC-
TC+
TCLK -
TCLK +
LV DS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLK I N
TC6
GND
N/C
THC63LVDM 83R THC63LVDM63R
PLL
TA +/-
TB +/-
TC +/-
TD +/-
TCLK +/-
R/F
/PDWN
TA0-6
TC0-6
TD0-6
TRANSMITTER
(20 to 85MHz)
CMOS/TTL
7
7
RS
7
TB0-6
7
INPUTS
CLOCK
(LVDS)
20-85MHz
DATA
(LVDS)
(140-595Mbit/On Each
LVDS Channel)
CLOCK IN
TT
L P
A
RA
LL
EL T
O
SE
RI
A
L
PLL
7
7
7
CMOS/TTL
INPUTS
TA0-6
TB0-6
TC0-6
TRANSMI TTER
(20 to 85MHz)
CLOCK IN
R/F
/PDWN
RS
TA +/-
TB +/-
TC +/-
TCLK +/-
CLOCK
(LVDS)
20-85MHz
(140-595Mbit/On Each
LVDS Channel)
THC63LVDM 83R
THC63LVDM 63R
DATA
(LVDS)
TT
L P
A
RA
LL
EL T
O
SE
RI
A
L
PIN CONFIGURATION
BLOCK DIAGRAM