3-17
6. µ
-COM Block Diagram
MPEG
I/F
FRONT
I/F
SERVO
I/F
DSP
I/F
D[00:07], A[00:02], IIC_CLK, IIC_DATA, SCLK0,
MPEG_INT
BCA_CODE SPINDLE_FG, SLD_FG,
D[00:07], A[00:05], E_SIN, E_CLK
LOAD FR, F/R, LOCK, DEFECT, FOK,
DSP_SENSE
8
D[00:07]
EXP_W2,
/PWR_CLT
D[00:15]
D[00:15]
D[00:15]
A[01:19]
A[19:21]
/IOCSI, /WR
SENS_MCOM,
MICOM_WAIT
2
2
D[00:04]
MICOM_RESET
PWR_CTL,
SENS, LIMIT_SW,
MIC_ON, CLOSE_SW,
OPEN_SW, MPEG_WAIT,
ZIERR
MPEG_ERROR,
DAC_L0,
RF_LAT,
/DSP_CS,
/MPEG_CS,
/PP_CS
6
8
2
2
A[01:09]
19
16
9
16
16
A[01:21] 21
2
MPEG_CTL,
E_DR,
/ZOOM_RST,
/S_XRST,
XLAT,
ACT_MUTE,
V_MUTE,
A_MUTE
8
IIC_CLK,
IIC_DATA
2
IC114
EEPROM
AT24C02
IC101
XC9536
IC106
ROM
512K x 16
IC102
74HC374
IC107
DRAM
256K x 16
IC108
SH7034
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