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Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
6. CIRCUIT DIAGRAM
L2100
82n
82n
L2101
L2102
82n
82n
L2103
C2104
22
p
22
p
C2105
C2106
22
p
22
p
C2107
VREF_LDO_MPP_3
R2110
3.9K TOL=0.01
TOL=0.01
240
R2102
R2104
240
TOL=0.01
C2101
0.1u
6.3V
R2106
0
R2107
0
C2102
DNI
C2103
DNI
VREG_L6_1V8
VREG_L7_1V9
MSM8226
U2100
AW28
AY27
AW26
AY25
P1
M1
L2
M5
L4
M3
G24
D23
E22
F21
K1
G2
D1
E4
J2
G4
E2
F3
G6
F1
U6
AN10
J30
AM29
P33
AF33
AP33
AW34
AR32
AY35
AN34
AT31
C34
AV31
AU32
E32
D33
B35
B27
L6
G20
P37
AP3
AR4
AM3
AN4
AE8
AC6
AD7
AA6
W2
Y1
AB3
AB5
R34
P35
V35
U34
U32
AE2
AF1
AF3
AF5
AG6
AG4
AH1
AG2
AU16
AR16
AW14
AY15
AR20
AP19
AV21
AT21
AT17
AV17
AT27
AV27
AR22
AU22
AW22
AY23
AN24
AP23
AR26
AU26
AY19
AD1
AM9
A22
B25
D27
G28
Y39
AC2
VREF_CA
VREF_DQ
PMIC_SPMI_CLK
PMIC_SPMI_DATA
HSIC_CAL
USB_HS2_REXT
EBI0_CAL_REXT
EBI0_ZQ0
EBI0_ZQ1
MIPI_CSI0_LN0_N
MIPI_CSI0_LN0_P
MIPI_CSI0_LN2_N
MIPI_CSI0_LN2_P
MIPI_CSI0_LN3_N
MIPI_CSI0_LN3_P
MIPI_CSI0_LN4_N
MIPI_CSI0_LN4_P
MIPI_CSI1_LN0_N
MIPI_CSI1_LN0_P
MIPI_DSI0_CLK_N
MIPI_DSI0_CLK_P
MIPI_DSI0_LN0_N
MIPI_DSI0_LN0_P
MIPI_DSI0_LN1_N
MIPI_DSI0_LN1_P
MIPI_DSI0_LN2_N
MIPI_DSI0_LN2_P
MIPI_DSI0_LN3_N
MIPI_DSI0_LN3_P
BBRX_CH0_IM
BBRX_CH0_IP
BBRX_CH0_QM
BBRX_CH0_QP
BBRX_CH1_IM
BBRX_CH1_IP
BBRX_CH1_QM
BBRX_CH1_QP
WLAN_REXT
WLAN_BB_IM
WLAN_BB_IP
WLAN_BB_QM
WLAN_BB_QP
TX_DAC0_IM
TX_DAC0_IP
TX_DAC0_QM
TX_DAC0_QP
TX_DAC0_IREF
TX_DAC1_QM
TX_DAC1_QP
TX_DAC1_IREF
GNSS_BB_IP
GNSS_BB_IM
GNSS_BB_QP
GNSS_BB_QM
WCN_XO
USB_HS2_SYSCLK
CXO
CXO_EN
SLEEP_CLK
RESIN_N
RESOUT_N
MODE_0
MODE_1
PS_HOLD
SRST_N
TCK
TDI
TDO
TMS
TRST_N
EBI0_VREF_D0
EBI0_VREF_D1
EBI0_VREF_D2
EBI0_VREF_D3
EBI0_VREF_CA
VREF_APC_MPM
SDC1_CLK
SDC1_CMD
SDC1_DATA_0
SDC1_DATA_1
SDC1_DATA_2
SDC1_DATA_3
SDC1_DATA_4
SDC1_DATA_5
SDC1_DATA_6
SDC1_DATA_7
USB_HS2_DM
USB_HS2_DP
USB_HS2_ID
USB_HS2_VBUS
QDSS_SDC2_TRCLK/SDC2_CLK
QDSS_SDC2_TRSYNC/SDC2_CMD
QDSS_SDC2_TRDATA_0/SDC2_DATA_0
QDSS_SDC2_TRDATA_1/SDC2_DATA_1
QDSS_SDC2_TRDATA_2/SDC2_DATA_2
QDSS_SDC2_TRDATA_0/SDC2_DATA_3
MIPI_CSI0_LN1_N/MIPI_CSI0_CLK_N
MIPI_CSI0_LN1_P/MIPI_CSI0_CLK_P
MIPI_CSI1_LN1_N/MIPI_CSI1_CLK_N
MIPI_CSI1_LN1_P/MIPI_CSI1__CLK_P
VREF_LPDDR2
C2100
0.1u
DNI
R2103
DNI
R2101
R2100
200
TOL=0.01
WFR_DRXBB_Q_P
WFR_DRXBB_I_P
WFR_DRXBB_I_N
WFR_DRXBB_Q_N
WTR0_PRXBB_Q_P
WTR0_PRXBB_Q_N
WTR0_PRXBB_I_P
WTR0_PRXBB_I_N
WTR0_GNSSBB_Q_N
WTR0_GNSSBB_I_N
WTR0_GNSSBB_Q_P
WTR0_GNSSBB_I_P
WLAN_I_P
WLAN_I_N
WLAN_Q_P
WLAN_Q_N
USB_D_M
USB_D_P
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
WTR0_DAC_IREF
WTR0_TXBB_Q_N
WTR0_TXBB_I_P
WTR0_TXBB_I_N
WTR0_TXBB_Q_P
BB_CLK
LCD_MIPI_CLK_P
LCD_MIPI_DATA0_P
LCD_MIPI_DATA0_N
LCD_MIPI_DATA1_N
LCD_MIPI_DATA1_P
LCD_MIPI_CLK_N
VT_CAM_MIPI_DATA0_N
VT_CAM_MIPI_CLK_P
VT_CAM_MIPI_CLK_N
VT_CAM_MIPI_DATA0_P
MAIN_CAM0_MIPI_CLK_P
MAIN_CAM0_MIPI_CLK_N
MAIN_CAM0_MIPI_DATA1_N
MAIN_CAM0_MIPI_DATA0_N
MAIN_CAM0_MIPI_DATA0_P
MAIN_CAM0_MIPI_DATA1_P
SLEEP_CLK
BB_CLK_EN
MSM_PS_HOLD
eMMC_CLK
JTAG_TRST
JTAG_SRST
SDCARD_DATA_2
SDCARD_CLK
SDCARD_CMD
SDCARD_DATA_3
SDCARD_DATA_0
SDCARD_DATA_1
MSM_RESOUT_N
eMMC_CMD
EMMC_DATA_0
EMMC_DATA_1
EMMC_DATA_3
EMMC_DATA_4
EMMC_DATA_5
EMMC_DATA_6
EMMC_DATA_7
PMIC_SPMI_DATA
PMIC_SPMI_CLK
MSM_RESIN_N
EMMC_DATA_2
If not use, floating
Ground both P37 and K37 if WCN3620
Refer to Ref. sch.
If DSDA, connect 3Pins to WTR2100
DNI
connect to WCN
GND
3.9k
R2110
IQ line
PIN
BCM using
WCN using
is used or if no WCN is used.
Rev_0.6
< 2-1-3-1-1_MSM8226_DATA >
Rev_0.4
Rev_0.4
ZQ1 line is needed for 3-die LPDDR2 package
W/X is used 2die LPDDR (256M32D2 )
05/30
Make sure that CXO is the last load
USB_HS2_SYSCLK is the first load on the CLK from PMIC
he only mode supported is MODE = 00, and both pins are internally pulled to GND by default.
An external pull for the MODE pins is not necessary.