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18
Notes :
•
LRCK, BCK and PCMD are changed to 32-bit slot and 48-bit slot by command.
32-bit slot is output in 2's complements on an LSB-first basis and 48-bit slot is output in 2's complements on
an MSB-first basis.
•
*'s signal is able to convert to output by a command. (Refer to sub CPU Register 08h (W) of decoder part)
•
The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.
•
XRAOF is a signal issued when a jitter margin of +28F is exceeded by the 32K RAM.
•
C2PO is a signal to indicate data error.
•
XUGF is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected.
Pin No.
Symbol
I/O
Description
114
VSIO5
Digital Power Supply GND
115
HDBD
I/O
1,Z,0
Host Data Bus
116
HDB2
I/O
1,Z,0
Host Data Bus
117
HDBC
I/O
1,Z,0
Host Data Bus
118
HDB3
I/O
1,Z,0
Host Data Bus
119
VDIO3
Digital Power Supply (3.3V)
120
HDBB
I/O
1,Z,0
Host Data Bus
121
HDB4
I/O
1,Z,0
Host Data Bus
122
HDBA
I/O
1,Z,0
Host Data Bus
123
HDB5
I/O
1,Z,0
Host Data Bus
124
VSIO4
Digital Power Supply GND
125
HDB9
I/O
1,Z,0
Host Data Bus
126
HDB6
I/O
1,Z,0
Host Data Bus
127
HDB8
I/O
1,Z,0
Host Data Bus
128
HDB7
I/O
1,Z,0
Host Data Bus
129
VDC3
Digital Power Supply (2.5V)
130
XTL2
O
1, 0
Crystal Oscillating Circuit Output of the Clock for Decoder
131
XTL1
I
Crystal Oscillating Circuit Input of the Clock for Decoder
132
VSC3
Digital GND
133
AVS3
Analog GND
134
PWM2N
O
1, 0
PWM Output of Audio DAC. Default R Ch, Reverse Phase
135
PWM2P
O
1, 0
PWM Output of Audio DAC. Default R Ch, Forward Phase
136
AVD3
Analog Power Supply (2.5V)
137
AVD4
Power Supply for Master Clock (2.5V)
138
XTLO
O
1,0
Crystal Oscillating Circuit Output for the Master Clock
139
XTLI
I
Crystal Oscillating Circuit Input for the Master Clock
140
AVS4
GND for the Master Clock
141
AVS5
Analog GND
142
PWM1P
O
1, 0
PWM Output of Audio DAC. L Ch, Forward Phase
143
PWM1N
O
1, 0
PWM Output of Audio DAC. L Ch, Reverse Phase
144
AVD5
Analog Power Supply (2.5V)