1Mbits DRAM
CLOCK
GEN
DATA
processor
DMA SEQUENCER
ADDRESS GEN
(Serial I/F)
CLOCK
GEN
PRIORITY RESOLVER
Subcode
Deinterleave & ECC
MAIN DATA
ERROR CORRECTION
ATAPI REGISTERS
12byte PACKET FIFO
HOST
I/F
DESCRAMBLER
SYNC CONTROL
Sub CPU I/F
DRVss
DRV
DD
HDB0~F
139~142,
145~148,
151~154,
156~159
HCS0,1
123~125
121,122
HA0~2
XHRD
XHWR
XHAC
HDRQ
HINT
XS16
REDY
D0~7*
A0~6*
DASP
XPDI
HAST
137
119
120
130
127
128
136
129
135
134
DMA FIFO
Digital OUT
8fs
1bit DAC
Error
Correction
block
Subcode P~W
Processor
32K RAM
EFM
Timing Generator
Subcode Q
Processor
XRD*
XWR*
XCS*
XTL
1
XINT*
XWAT*
XTL
2
PWM2N
PWM2P
FOK
PWM1N
175
167
166
161
162
PWM1P
MIRR
DFCT
174
OP Amp
DAC
SERVO DSP
Auto Sequencer
8bit
A/D
OP Amp
Analog SW
SAO
TAO
FAO
BSSD
DOUT
DAC
I/F
CD-DSP
I/F
CPU Interface
FOK
MIRR
DFCT
XTLO
XTLI
170
171
Digital PLL
ASY
Sync protector
PCO
V
DD
Vss
52
FILI
51
FILO
50
CLTV
53
ASYI
57
ASYO
58
WFCK
SCOR*
29
RFDC
CE
TE
SE
FE
VC
SQCK*
SQSO*
SENS*
COUT*
MDP
PWMI
ADIO
RFAC
55
CLV/CAV
Processor
SERVO BLOCK
DAC BLOCK
DATA BLOCK
19
20
41
42
43
44
45
46
47
5
4
3
2
21
65
64
16
15
• IC501 (CXD3035R) : DSP+ATAPI DRAM+µ-COM
Block Diagram
*
is connected to µ-com port inside.