IC301 (MB90F476) : MICOM
Block Diagram
42
PPG0, 1
Interrupt controller
2
8-/16-bit PPG
8-/16-bit UD counter
Chip select
I/O timer
16-bit input capture x2
16-bit output conveyer x6
16-bit free-run timer
16-bit reload timer
x2 channels
A/D converter
(10 bits)
I/O expanded
serial
interface x2
channels
UART
Communication
prescaler
µ
DMA
ROM
RAM
Clock control
circuit
X0, X1 RSTX
X0, X1A
5
CPU
F MC-16LX family Core
External interrupt
I/O port
P00
P07
PPG2, 3
PPG4, 5
AVCC
SIN1, 2
SOT1, 2
AVRH.L
AVSS
ADTG
AN0 to 7
CS0, 1, 2, 3
OUT0, 1, 2,
3, 4, 5
AIN0, 1
BIN0, 1
SCK1, 2
SIN0
SOT0
SCK0
ZIN0, 1
IN0, 1
TOT0
TIN0
IRQ0 to 7
8
8
2
P10
P17
8
P20
P27
8
P30
P37
8
P40
P47
8
P50
P57
8
P60
P67
8
P70
P77
8
P80
P87
8
P90
P97
8
PA0
PA3
4
P00 to P07 (8) : Provided with input pull-up resistor setting register
P10 to P17 (8) : Provided with input pull-up resistor setting register
P40 to P47 (8) : Provided with open-drain setting register
P70 to P77 (6) : Provided with open-drain setting register
*
NOTE
: In the figure above, the I/O port shares the pins each internal functional block. When the pins are used
as internal module pins, they cannot be used as I/O port pins.