LG 79UB980T, Service Manual

Page: 29 / 111

THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M1_DDR_DQ16
M0_DDR_A14
M1_DDR_A2
C511
22uF
10V
M0_U_CLKN
M1_DDR_BA1
M1_DDR_DM1
R559
240
1%
M0_DDR_A1
M1_DDR_DM3
M0_DDR_A8
VDDC15_M0
M0_U_CLKN
M0_DDR_DQ1
M0_DDR_ODT
M1_DDR_DQ10
M0_U_CLK
M1_DDR_DQ5
M0_DDR_A11
M1_DDR_DQ27
M1_DDR_DQ17
M0_DDR_RASN
M0_DDR_WEN
M0_DDR_CASN
AR10
56
M0_DDR_DQ12
M0_DDR_CKE
M1_DDR_DQS2
M0_DDR_A12
M0_DDR_A15
M0_DDR_DQ17
M1_DDR_DM0
M0_DDR_DQ26
M0_U_CLK
C521
0.1uF
16V
M0_DDR_DQ3
M0_DDR_A1
VDDC15_M1
M1_DDR_DQ13
M0_DDR_DQ23
R532
1K
1%
R538
1K
1%
M1_DDR_A5
M1_DDR_A6
M1_DDR_DQ19
M0_DDR_A13
C550
0.1uF
C513
0.1uF
M1_DDR_A13
AR12
56
M1_DDR_DQ26
R552
1K
1%
M0_D_CLK
M0_DDR_A13
M0_DDR_DQ19
M0_DDR_DQ5
+3.3V_NORMAL
M1_DDR_BA2
M1_DDR_DM1
M0_DDR_DQ27
H5TQ4G83AFR-PBC
IC500
A0
K3
A1
L7
A2
L3
A3
K2
A4
L8
A5
L2
A6
M8
A7
M2
A8
N8
A9
M3
A10/AP
H7
A11
M7
A12/BC
K7
A13
N3
BA0
J2
BA1
K8
BA2
J3
CK
F7
CK
G7
CKE
G9
CS
H2
ODT
G1
RAS
F3
CAS
G3
WE
H3
RESET
N2
DQS
C3
DQS
D3
DM/TDQS
B7
NF/TDQS
A7
DQ0
B3
DQ1
C7
DQ2
C2
DQ3
C8
DQ4
E3
DQ5
E8
DQ6
D2
DQ7
E7
NC_1
A3
NC_2
F1
NC_3
F9
NC_4
H1
NC_5
H9
A15
J7
VREFCA
J8
VREFDQ
E1
ZQ
H8
VDD_1
A2
VDD_2
A9
VDD_3
D7
VDD_4
G2
VDD_5
G8
VDD_6
K1
VDD_7
K9
VDD_8
M1
VDD_9
M9
VDDQ_1
B9
VDDQ_2
C1
VDDQ_3
E2
VDDQ_4
E9
VSS_1
A1
VSS_2
A8
VSS_3
B1
VSS_4
D8
VSS_5
F2
VSS_6
F8
VSS_7
J1
VSS_8
J9
VSS_9
L1
VSS_10
L9
VSS_11
N1
VSS_12
N9
VSSQ_1
B2
VSSQ_2
B8
VSSQ_3
C9
VSSQ_4
D1
VSSQ_5
D9
A14
N7
M0_DDR_DQS_N1
M1_DDR_A8
M0_D_CLK
VDDC15_M0
C568 0.1uF
C559
0.1uF
M1_DDR_BA2
M0_DDR_A11
M1_DDR_DQ11
M1_DDR_A12
VDDC15_M1
M0_1_DDR_VREFCA
M1_DDR_DQ12
M0_DDR_DM3
M0_DDR_A14
M0_DDR_DQ13
M0_D_CLKN
C501
0.1uF
M0_DDR_DQ6
IC100
LG1154D_H13D
M0_DDR_A[0]
F15
M0_DDR_A[1]
F13
M0_DDR_A[2]
F17
M0_DDR_A[3]
F19
M0_DDR_A[4]
E10
M0_DDR_A[5]
E18
M0_DDR_A[6]
E11
M0_DDR_A[7]
F18
M0_DDR_A[8]
F11
M0_DDR_A[9]
F16
M0_DDR_A[10]
E9
M0_DDR_A[11]
E12
M0_DDR_A[12]
E13
M0_DDR_A[13]
E16
M0_DDR_A[14]
F12
M0_DDR_A[15]
F14
M0_DDR_BA[0]
E19
M0_DDR_BA[1]
F10
M0_DDR_BA[2]
E15
M0_DDR_U_CLK
B10
M0_DDR_U_CLKN
A10
M0_DDR_D_CLK
A19
M0_DDR_D_CLKN
B19
M0_DDR_CKE
E14
M0_DDR_ODT
F21
M0_DDR_RASN
E21
M0_DDR_CASN
E20
M0_DDR_WEN
F20
M0_DDR_RESET_N
E17
M0_DDR_ZQCAL
F9
M0_DDR_DQS[0]
B20
M0_DDR_DQS_N[0]
A20
M0_DDR_DQS[1]
C19
M0_DDR_DQS_N[1]
D19
M0_DDR_DQS[2]
A11
M0_DDR_DQS_N[2]
B11
M0_DDR_DQS[3]
C10
M0_DDR_DQS_N[3]
D10
M0_DDR_DM[0]
D18
M0_DDR_DM[1]
C20
M0_DDR_DM[2]
D9
M0_DDR_DM[3]
C11
M0_DDR_DQ[0]
D22
M0_DDR_DQ[1]
C15
M0_DDR_DQ[2]
C23
M0_DDR_DQ[3]
D16
M0_DDR_DQ[4]
B24
M0_DDR_DQ[5]
B15
M0_DDR_DQ[6]
D23
M0_DDR_DQ[7]
A15
M0_DDR_DQ[8]
C16
M0_DDR_DQ[9]
D21
M0_DDR_DQ[10]
D17
M0_DDR_DQ[11]
C22
M0_DDR_DQ[12]
C18
M0_DDR_DQ[13]
C21
M0_DDR_DQ[14]
C17
M0_DDR_DQ[15]
D20
M0_DDR_DQ[16]
C13
M0_DDR_DQ[17]
D7
M0_DDR_DQ[18]
D13
M0_DDR_DQ[19]
C6
M0_DDR_DQ[20]
D14
M0_DDR_DQ[21]
D6
M0_DDR_DQ[22]
C14
M0_DDR_DQ[23]
A5
M0_DDR_DQ[24]
C7
M0_DDR_DQ[25]
D12
M0_DDR_DQ[26]
D8
M0_DDR_DQ[27]
B13
M0_DDR_DQ[28]
C9
M0_DDR_DQ[29]
C12
M0_DDR_DQ[30]
C8
M0_DDR_DQ[31]
D11
M0_DDR_WEN
C506
10uF
M0_DDR_DQ10
M0_DDR_A2
M1_DDR_A6
M1_DDR_A13
M1_DDR_A4
M0_DDR_DQ5
M1_DDR_DQ1
H5TQ4G63AFR-PBC
IC503-*1
DDR_HYNIX
A0 N3
A1 P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7 R2
A8 T8
A9 R3
A10/AP L7
A11 R7
A12/BC
N7
A13
T3
A15
M7
BA0 M2
BA1 N8
BA2 M3
CK J7
CK
K7
CKE
K9
CS
L2
ODT K1
RAS J3
CAS K3
WE L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU C7
DQSU B7
DML E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3 F8
DQL4 H3
DQL5 H8
DQL6 G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3 C2
DQU4 A7
DQU5 A2
DQU6 B8
DQU7 A3
VREFCA M8
VREFDQ
H1
ZQ
L8
VDD_1 B2
VDD_2 D9
VDD_3 G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9 R9
VDDQ_1 A1
VDDQ_2 A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7 F1
VDDQ_8 H2
VDDQ_9 H9
NC_1 J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1 A9
VSS_2 B3
VSS_3 E1
VSS_4 G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10 P9
VSS_11 T1
VSS_12 T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5 E2
VSSQ_6 E8
VSSQ_7 F9
VSSQ_8 G1
VSSQ_9 G9
M1_DDR_DQ14
M1_DDR_CKE
M0_DDR_BA0
M0_DDR_DQS2
M0_DDR_RESET_N
M1_DDR_RESET_N
R512
1K
1%
M1_DDR_DQ28
M0_DDR_DQ0
M1_DDR_A3
M0_DDR_A10
C510
1000pF
M1_DDR_A5
M0_DDR_VREFCA_T
M1_DDR_VREFDQ
M1_DDR_WEN
M1_DDR_DQ8
M1_DDR_DQ10
M0_D_CLK
M0_U_CLK
M0_DDR_A6
R537
1K
1%
M1_DDR_DQ25
M0_DDR_A11
R
5
1
9
2
0
0
M1_1_DDR_VREFCA
M1_DDR_BA0
M0_DDR_DQ9
M0_DDR_VREFCA
M0_DDR_BA2
M0_DDR_DQ22
M0_DDR_BA1
M1_DDR_A8
M1_DDR_DQ24
R511
1K
1%
M0_DDR_CASN
VDDC15_M1
M0_DDR_A13
C561 0.1uF
M0_DDR_A0
M0_DDR_A5
M1_DDR_A5
M0_DDR_BA0
M1_DDR_A14
M1_U_CLKN
M1_DDR_WEN
M0_DDR_DQS1
M0_DDR_CASN
R546
10K 1%
M1_DDR_BA1
M0_DDR_DQS_N1
M0_DDR_A11
R500 240
1%
M0_DDR_DQ31
M1_DDR_A0
M1_DDR_DQS_N1
M1_DDR_DQ30
M1_DDR_DQS1
M0_DDR_RASN
VDDC15_M0
M0_DDR_A4
M0_DDR_CKE
M0_DDR_A12
M0_DDR_DQ2
M0_DDR_DQ8
M1_DDR_CASN
M1_DDR_BA2
VDDC15_M1
M0_DDR_DQS_N3
R545 240
R555
1K
1%
M1_DDR_DQ20
M1_DDR_A1
M0_DDR_A7
R516
1K
1%
M0_DDR_A0
M1_DDR_DQ6
M1_DDR_BA1
M0_DDR_A12
M0_U_CLKN
M1_DDR_A3
C500
0.1uF
M0_DDR_DQS_N0
R556
1K
1%
R543 240
M0_DDR_CKE
M1_DDR_A3
M0_DDR_DQ26
M0_DDR_A15
M1_DDR_A12
M1_DDR_RASN
VDDC15_M0
M1_DDR_RESET_N
M1_DDR_DM2
M1_DDR_A0
C505
0.1uF
M1_DDR_RESET_N
R561
240
1%
M1_DDR_DQ7
M1_DDR_DQ29
M0_DDR_BA2
M0_DDR_A4
M1_DDR_A7
R3104
56
VDDC15_M0
R557
1K
1%
M1_DDR_DQS1
K4B4G1646B-HCK0
IC503
DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M1_DDR_DQ17
AR11
56
M1_DDR_A15
M1_DDR_DQ6
M1_U_CLK
M0_DDR_BA0
R520
10K
M1_DDR_DQ29
M1_D_CLK
M1_DDR_A11
M1_DDR_A4
C572 0.1uF
R558
240
1%
M1_DDR_A7
M0_DDR_DM1
C514
0.1uF
L500
UBW2012-121F
M0_DDR_DQ18
R
5
1
8
1
0
0
C515
4700pF
M0_DDR_BA2
M0_D_CLK
M0_DDR_DQ7
M0_DDR_A7
AR7
56
C583 0.1uF
M0_DDR_A14
R521
10K
M0_D_CLKN
M0_DDR_BA2
M0_DDR_BA0
M0_DDR_BA0
C530
0.1uF
C569 0.1uF
M0_DDR_A12
C504
0.1uF
M0_DDR_A3
M0_DDR_A15
H5TQ4G63AFR-PBC
IC501-*1
DDR_HYNIX
A0
N3
A1
P7
A2 P3
A3 N2
A4 P8
A5 P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11 R7
A12/BC N7
A13 T3
A15 M7
BA0
M2
BA1
N8
BA2
M3
CK J7
CK K7
CKE K9
CS L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET T2
DQSL F3
DQSL
G3
DQSU
C7
DQSU
B7
DML E7
DMU D3
DQL0 E3
DQL1 F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7 H7
DQU0 D7
DQU1 C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7 A3
VREFCA
M8
VREFDQ H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3 G7
VDD_4 K2
VDD_5 K8
VDD_6 N1
VDD_7 N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2 A8
VDDQ_3 C1
VDDQ_4 C9
VDDQ_5 D2
VDDQ_6 E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1 J1
NC_2 J9
NC_3 L1
NC_4 L9
A14 T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4 G8
VSS_5 J2
VSS_6 J8
VSS_7 M1
VSS_8 M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1 B1
VSSQ_2 B9
VSSQ_3 D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9 G9
M1_D_CLK
M1_DDR_DQ12
R560
240
1%
M1_DDR_DQS2
M0_DDR_DM0
M1_DDR_DQS3
M1_DDR_DQS0
M1_DDR_A6
M1_DDR_DQ30
M0_DDR_A0
M1_DDR_A11
M1_DDR_DQ3
M0_DDR_WEN
M0_D_CLKN
M1_DDR_BA0
M1_DDR_A8
M1_DDR_DQ18
R
5
3
5
2
0
0
M0_DDR_DM2
M0_DDR_DQ16
M0_DDR_A1
VDDC15_M0
M1_U_CLK
M0_DDR_A6
VDDC15_M0
IC506
TPS51200DRCR
3
VO
2
VLDOIN
4
PGND
1
REFIN
5
VOSNS
6
REFOUT
7
EN
8
GND
9
PGOOD
10
VIN
11
[EP]
M0_DDR_A2
M0_DDR_DQS0
M0_DDR_BA1
M0_DDR_DQS2
M0_DDR_ODT
M1_DDR_DQS_N3
M0_DDR_ODT
R539
1K
1%
C522
0.1uF
16V
M1_DDR_DQ22
M0_DDR_A15
M0_1_DDR_VREFDQ_T
M0_DDR_A11
M1_DDR_DQS_N2
M0_DDR_A3
M0_DDR_DQ1
M1_DDR_A14
M0_DDR_DQS0
M0_DDR_DQ29
M1_DDR_DQ15
M0_DDR_DQS_N2
M0_DDR_DQ17
M1_DDR_DQ8
M1_DDR_DQ14
M0_DDR_DQ14
M1_DDR_DQ4
M0_DDR_A3
M1_DDR_A10
M1_DDR_A9
R513
1K
1%
M1_DDR_DM0
M0_DDR_A9
M0_DDR_CKE
M1_D_CLK
M1_DDR_DQ21
C503
10uF
M0_DDR_DQ30
K4B4G1646B-HCK0
IC501
DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_DQ28
M1_DDR_A14
M1_DDR_VREFDQ
M1_DDR_CASN
M0_DDR_A5
M1_DDR_DQ9
M1_DDR_ODT
VDDC15_M0
M1_DDR_DQ15
M0_DDR_DQS3
M0_1_DDR_VREFDQ_T
M0_DDR_RESET_N
M1_DDR_DQ5
M0_DDR_DM0
M1_DDR_DQ1
M1_D_CLKN
M1_DDR_DM2
M1_DDR_CKE
R
5
8
1
2
0
0
M0_DDR_A2
M0_DDR_DQ6
M0_D_CLKN
H5TQ4G83AFR-PBC
IC502
A0
K3
A1
L7
A2
L3
A3
K2
A4
L8
A5
L2
A6
M8
A7
M2
A8
N8
A9
M3
A10/AP
H7
A11
M7
A12/BC
K7
A13
N3
BA0
J2
BA1
K8
BA2
J3
CK
F7
CK
G7
CKE
G9
CS
H2
ODT
G1
RAS
F3
CAS
G3
WE
H3
RESET
N2
DQS
C3
DQS
D3
DM/TDQS
B7
NF/TDQS
A7
DQ0
B3
DQ1
C7
DQ2
C2
DQ3
C8
DQ4
E3
DQ5
E8
DQ6
D2
DQ7
E7
NC_1
A3
NC_2
F1
NC_3
F9
NC_4
H1
NC_5
H9
A15
J7
VREFCA
J8
VREFDQ
E1
ZQ
H8
VDD_1
A2
VDD_2
A9
VDD_3
D7
VDD_4
G2
VDD_5
G8
VDD_6
K1
VDD_7
K9
VDD_8
M1
VDD_9
M9
VDDQ_1
B9
VDDQ_2
C1
VDDQ_3
E2
VDDQ_4
E9
VSS_1
A1
VSS_2
A8
VSS_3
B1
VSS_4
D8
VSS_5
F2
VSS_6
F8
VSS_7
J1
VSS_8
J9
VSS_9
L1
VSS_10
L9
VSS_11
N1
VSS_12
N9
VSSQ_1
B2
VSSQ_2
B8
VSSQ_3
C9
VSSQ_4
D1
VSSQ_5
D9
A14
N7
R550
1K
1%
M1_DDR_DQS_N0
M1_U_CLKN
M0_DDR_A13
IC100
LG1154D_H13D
M1_DDR_A[0]
N6
M1_DDR_A[1]
R6
M1_DDR_A[2]
L6
M1_DDR_A[3]
J6
M1_DDR_A[4]
U5
M1_DDR_A[5]
J5
M1_DDR_A[6]
T5
M1_DDR_A[7]
K6
M1_DDR_A[8]
U6
M1_DDR_A[9]
M6
M1_DDR_A[10]
V5
M1_DDR_A[11]
R5
M1_DDR_A[12]
P5
M1_DDR_A[13]
L5
M1_DDR_A[14]
T6
M1_DDR_A[15]
P6
M1_DDR_BA[0]
H5
M1_DDR_BA[1]
V6
M1_DDR_BA[2]
M5
M1_DDR_U_CLK
R2
M1_DDR_U_CLKN
R1
M1_DDR_D_CLK
F1
M1_DDR_D_CLKN
F2
M1_DDR_CKE
N5
M1_DDR_ODT
G6
M1_DDR_RASN
F5
M1_DDR_CASN
G5
M1_DDR_WEN
H6
M1_DDR_RESET_N
K5
M1_DDR_ZQCAL
F6
M1_DDR_DQS[0]
E2
M1_DDR_DQS_N[0]
E1
M1_DDR_DQS[1]
F3
M1_DDR_DQS_N[1]
F4
M1_DDR_DQS[2]
P1
M1_DDR_DQS_N[2]
P2
M1_DDR_DQS[3]
R3
M1_DDR_DQS_N[3]
R4
M1_DDR_DM[0]
G4
M1_DDR_DM[1]
E3
M1_DDR_DM[2]
T4
M1_DDR_DM[3]
P3
M1_DDR_DQ[0]
C4
M1_DDR_DQ[1]
K3
M1_DDR_DQ[2]
B3
M1_DDR_DQ[3]
J4
M1_DDR_DQ[4]
A3
M1_DDR_DQ[5]
K2
M1_DDR_DQ[6]
B4
M1_DDR_DQ[7]
K1
M1_DDR_DQ[8]
J3
M1_DDR_DQ[9]
D4
M1_DDR_DQ[10]
H4
M1_DDR_DQ[11]
C3
M1_DDR_DQ[12]
G3
M1_DDR_DQ[13]
D3
M1_DDR_DQ[14]
H3
M1_DDR_DQ[15]
E4
M1_DDR_DQ[16]
M3
M1_DDR_DQ[17]
V4
M1_DDR_DQ[18]
M4
M1_DDR_DQ[19]
W3
M1_DDR_DQ[20]
L4
M1_DDR_DQ[21]
W4
M1_DDR_DQ[22]
L3
M1_DDR_DQ[23]
Y2
M1_DDR_DQ[24]
V3
M1_DDR_DQ[25]
N4
M1_DDR_DQ[26]
U4
M1_DDR_DQ[27]
M2
M1_DDR_DQ[28]
T3
M1_DDR_DQ[29]
N3
M1_DDR_DQ[30]
U3
M1_DDR_DQ[31]
P4
M0_DDR_DQ4
M0_DDR_DQ11
M0_DDR_CASN
M1_DDR_CKE
M1_DDR_A13
M0_DDR_DQ21
M1_DDR_BA0
M0_DDR_A2
M1_DDR_RASN
M0_DDR_VREFCA
M0_DDR_A10
C553
0.1uF
M0_DDR_DQ13
M1_U_CLK
M0_U_CLK
M0_DDR_DQS_N3
M0_DDR_BA2
C529
0.1uF
M0_DDR_WEN
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_A4
M0_DDR_A1
R549
10K
1%
M0_DDR_BA1
VDDC15_M0
M1_DDR_DQ0
M0_DDR_A9
M0_DDR_DQ24
M1_DDR_DQ2
M0_DDR_WEN
M0_DDR_VREFCA_T
M0_DDR_A8
C509
0.1uF
M1_U_CLKN
M0_DDR_DM2
M0_DDR_DQ21
VDDC15_M0
M0_DDR_VREFDQ
M0_DDR_A10
M1_DDR_A15
M0_DDR_CASN
M1_DDR_DQ13
M0_DDR_CKE
M1_DDR_A9
VDDC15_M0
M1_DDR_DQ23
M1_DDR_DQS_N1
R534
1K
1%
M0_DDR_VREFDQ_T
M0_DDR_A8
M0_DDR_DQ31
M1_DDR_DQ28
M0_DDR_DQ4
AR8
56
M1_DDR_DQ4
M1_DDR_DQ9
M0_DDR_A10
M1_DDR_DQ24
M0_DDR_DQ14
M0_DDR_A5
R540
10K
M0_1_DDR_VREFCA
C519
0.1uF
16V
M0_DDR_DQ12
M1_DDR_CASN
M0_DDR_RESET_N
M1_DDR_DQ31
M1_DDR_A15
M1_DDR_A0
M1_DDR_DM3
M1_DDR_DQ16
M0_DDR_A4
M0_DDR_DQ20
C507
10uF
R510
1K
1%
M0_DDR_DQ8
M0_DDR_A3
C577 0.1uF
R553
1K
1%
M1_DDR_A9
M0_DDR_RESET_N
R541
10K
M1_DDR_DQ11
M0_DDR_RESET_N
AR9
56
M1_DDR_DQ19
M0_DDR_A6
M0_DDR_ODT
DDR_VTT
M1_DDR_WEN
M0_DDR_DQ0
VDDC15_M1
M0_DDR_DQ27
M1_DDR_DQ18
M1_D_CLKN
M1_DDR_VREFCA
M0_DDR_A0
R536
1K
1%
M0_1_DDR_VREFDQ
M0_DDR_DQ30
M1_D_CLKN
M0_DDR_A4
M0_DDR_A7
M0_DDR_DQ9
M0_DDR_A6
M0_DDR_DQ22
M0_DDR_RASN
M1_DDR_RASN
M1_DDR_A11
M0_DDR_DQ19
M0_DDR_DQ2
C520
0.1uF
16V
M1_DDR_DQS_N3
R531
1K
1%
M1_DDR_A7
M0_DDR_DQ10
M0_DDR_RASN
M1_DDR_DQ20
M0_DDR_A0
M0_DDR_DQ25
R515
1K
1%
M0_DDR_DQ20
M0_1_DDR_VREFCA_T
M1_1_DDR_VREFDQ
M1_DDR_A1
VDDC15_M0
M1_DDR_DQ2
M0_DDR_A15
M0_DDR_DQ7
R533
1K
1%
M0_DDR_VREFDQ_T
M0_DDR_DQ23
M0_D_CLK
M0_DDR_A14
M0_DDR_DQ15
M0_DDR_A14
M0_DDR_DQ11
VDDC15_M1
M0_DDR_BA1
C551
0.1uF
R
5
8
0
2
0
0
M0_DDR_DQ3
M1_DDR_ODT
C508
0.1uF
M1_DDR_DQ23
M1_DDR_ODT
M1_DDR_DQS_N2
VDDC15_M0
M0_DDR_A6
H5TQ4G83AFR-PBC
IC504
A0
K3
A1
L7
A2
L3
A3
K2
A4
L8
A5
L2
A6
M8
A7
M2
A8
N8
A9
M3
A10/AP
H7
A11
M7
A12/BC
K7
A13
N3
BA0
J2
BA1
K8
BA2
J3
CK
F7
CK
G7
CKE
G9
CS
H2
ODT
G1
RAS
F3
CAS
G3
WE
H3
RESET
N2
DQS
C3
DQS
D3
DM/TDQS
B7
NF/TDQS
A7
DQ0
B3
DQ1
C7
DQ2
C2
DQ3
C8
DQ4
E3
DQ5
E8
DQ6
D2
DQ7
E7
NC_1
A3
NC_2
F1
NC_3
F9
NC_4
H1
NC_5
H9
A15
J7
VREFCA
J8
VREFDQ
E1
ZQ
H8
VDD_1
A2
VDD_2
A9
VDD_3
D7
VDD_4
G2
VDD_5
G8
VDD_6
K1
VDD_7
K9
VDD_8
M1
VDD_9
M9
VDDQ_1
B9
VDDQ_2
C1
VDDQ_3
E2
VDDQ_4
E9
VSS_1
A1
VSS_2
A8
VSS_3
B1
VSS_4
D8
VSS_5
F2
VSS_6
F8
VSS_7
J1
VSS_8
J9
VSS_9
L1
VSS_10
L9
VSS_11
N1
VSS_12
N9
VSSQ_1
B2
VSSQ_2
B8
VSSQ_3
C9
VSSQ_4
D1
VSSQ_5
D9
A14
N7
M1_DDR_DQS_N0
M0_DDR_BA1
M0_DDR_DQS_N2
M1_DDR_A2
M0_DDR_DQS1
M0_DDR_A13
M0_DDR_ODT
R
5
3
0
1
0
0
M0_DDR_DQ29
M0_DDR_A4
C560
0.1uF
M0_DDR_A7
M0_DDR_VREFDQ
M1_DDR_CKE
M1_DDR_DQ21
M0_DDR_A10
M1_DDR_A12
M0_DDR_DQ24
R514
1K
1%
M0_U_CLKN
M0_DDR_A5
C562 0.1uF
M1_DDR_DQS3
M1_DDR_A1
M0_1_DDR_VREFCA_T
M0_D_CLKN
VDDC15_M0
C512
0.1uF
R517
1K
1%
M0_DDR_A8
M1_1_DDR_VREFDQ
M0_DDR_A9
VDDC15_M1
R554
1K
1%
M1_DDR_DQ7
M1_DDR_DQ27
M0_DDR_RASN
M0_DDR_DQS_N0
M0_DDR_A9
M1_DDR_VREFCA
M1_DDR_A10
M0_DDR_A1
L501
UBW2012-121F
M0_DDR_A5
M0_DDR_A12
M0_DDR_A7
M0_DDR_DQ28
M0_U_CLKN
M1_DDR_DQS0
C574 0.1uF
R551
1K
1%
M0_DDR_A2
M0_DDR_DM3
M1_1_DDR_VREFCA
M0_DDR_A9
M1_DDR_DQ0
M0_1_DDR_VREFDQ
DDR_VTT
M1_DDR_DQ31
M1_DDR_DQ22
M0_DDR_A3
M1_DDR_A10
M1_DDR_DQ3
M0_DDR_DQ18
M0_DDR_RESET_N
R501 240
1%
M0_DDR_DQ15
M1_DDR_RESET_N
M0_DDR_CKE
H5TQ4G83AFR-PBC
IC505
A0
K3
A1
L7
A2
L3
A3
K2
A4
L8
A5
L2
A6
M8
A7
M2
A8
N8
A9
M3
A10/AP
H7
A11
M7
A12/BC
K7
A13
N3
BA0
J2
BA1
K8
BA2
J3
CK
F7
CK
G7
CKE
G9
CS
H2
ODT
G1
RAS
F3
CAS
G3
WE
H3
RESET
N2
DQS
C3
DQS
D3
DM/TDQS
B7
NF/TDQS
A7
DQ0
B3
DQ1
C7
DQ2
C2
DQ3
C8
DQ4
E3
DQ5
E8
DQ6
D2
DQ7
E7
NC_1
A3
NC_2
F1
NC_3
F9
NC_4
H1
NC_5
H9
A15
J7
VREFCA
J8
VREFDQ
E1
ZQ
H8
VDD_1
A2
VDD_2
A9
VDD_3
D7
VDD_4
G2
VDD_5
G8
VDD_6
K1
VDD_7
K9
VDD_8
M1
VDD_9
M9
VDDQ_1
B9
VDDQ_2
C1
VDDQ_3
E2
VDDQ_4
E9
VSS_1
A1
VSS_2
A8
VSS_3
B1
VSS_4
D8
VSS_5
F2
VSS_6
F8
VSS_7
J1
VSS_8
J9
VSS_9
L1
VSS_10
L9
VSS_11
N1
VSS_12
N9
VSSQ_1
B2
VSSQ_2
B8
VSSQ_3
C9
VSSQ_4
D1
VSSQ_5
D9
A14
N7
M0_DDR_DM1
C552
0.1uF
M0_DDR_DQ16
M0_DDR_DQ25
DDR_VTT
M0_U_CLK
M0_DDR_DQS3
M1_DDR_A2
M0_DDR_A8
VDDC15_M1
C516
1uF
C502
1uF
MAIN DDR
2013-12-17
BSD-14Y-UD-005-HD
DDR3 1.5V bypass Cap - Place these caps near Memory
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
4Gbit : T7(A14)
DDR3 1.5V bypass Cap - Place these caps near Memory
1Gbit : T7(NC_6)
DDR3
4Gbit
Real USE : 1Gbit
DDR3
4Gbit
DDR3
4Gbit
DDR3
4Gbit
* DDR_VTT
Close to REFOUT pin
H5TQ1G63DFR-PBC(x16)
Place at the bottom side
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only