LG 65UX340C Series, Service Manual, Page: 43 / 46

THERMAL
MIU1 (U11 ONLY)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
A_DDR3_DQ[28]
A_DDR3_DQ[29]
A_DDR3_DQ[30]
A_DDR3_DQ[31]
A_DDR3_DQ[16]
A_DDR3_DQ[17]
A_DDR3_DQ[18]
A_DDR3_DQ[19]
A_DDR3_DQ[20]
A_DDR3_DQ[21]
A_DDR3_DQ[22]
A_DDR3_DQ[23]
A_DDR3_DQ[24]
A_DDR3_DQ[25]
A_DDR3_DQ[26]
A_DDR3_DQ[27]
A_DDR3_DQ[15]
A_DDR3_DQ[14]
A_DDR3_DQ[13]
A_DDR3_DQ[12]
A_DDR3_DQ[11]
A_DDR3_DQ[10]
A_DDR3_DQ[9]
A_DDR3_DQ[8]
A_DDR3_DQ[7]
A_DDR3_DQ[6]
A_DDR3_DQ[0]
A_DDR3_DQ[1]
A_DDR3_DQ[2]
A_DDR3_DQ[3]
A_DDR3_DQ[4]
A_DDR3_DQ[5]
A_DDR3_DQ[31]
A_DDR3_DQ[15]
A_DDR3_DQ[6]
A_DDR3_DQ[28]
A_DDR3_DQ[16]
A_DDR3_DQ[9]
A_DDR3_DQ[13]
A_DDR3_DQ[26]
A_DDR3_DQ[22]
A_DDR3_DQ[0]
A_DDR3_DQ[8]
A_DDR3_DQ[25]
A_DDR3_DQ[12]
A_DDR3_DQ[5]
A_DDR3_DQ[1]
A_DDR3_DQ[20]
A_DDR3_DQ[3]
A_DDR3_DQ[17]
A_DDR3_DQ[29]
A_DDR3_DQ[19]
A_DDR3_DQ[18]
A_DDR3_DQ[4]
A_DDR3_DQ[10]
A_DDR3_DQ[30]
A_DDR3_DQ[7]
A_DDR3_DQ[21]
A_DDR3_DQ[2]
A_DDR3_DQ[14]
A_DDR3_DQ[11]
A_DDR3_DQ[24]
A_DDR3_DQ[23]
A_DDR3_DQ[27]
B-MVREFDQ_U
R1382 240
1%
R1381 240
1%
A-MVREFDQ_U
A_DDR3_A[14]
A_DDR3_DQS3
A_DDR3_A[13]
A_DDR3_BA[1]
A_DDR3_CASZ
A_DDR3_DM1
A_DDR3_CSB2
A_DDR3_A[4]
A_DDR3_RASZ
A_DDR3_DQ[16-31]
A_DDR3_A[6]
A_DDR3_DM0
A_DDR3_DQS1
A_DDR3_A[0]
A_DDR3_BA[0]
A_DDR3_MCLKZ
A_DDR3_A[10]
A_DDR3_A[11]
A_DDR3_A[5]
A_DDR3_DQS1B
A_DDR3_DM2
A_DDR3_ODT
A_DDR3_A[9]
A_DDR3_DM3
A_DDR3_A[15]
A_DDR3_DQS0B
A_DDR3_A[1]
A_DDR3_DQS3B
A_DDR3_A[3]
A_DDR3_A[8]
A_DDR3_DQ[0-15]
A_DDR3_WEZ
A_DDR3_MCLK
A_DDR3_A[7]
A_DDR3_BA[2]
A_DDR3_RESET
A_DDR3_DQS2B
A_DDR3_CSB1
A_DDR3_DQS0
A_DDR3_A[12]
A_DDR3_DQS2
A_DDR3_CKE
A_DDR3_A[2]
AR13104
100
100ohm_DDR_VTT
A_DDR3_DM3
A_DDR3_RESET
A_DDR3_A[3]
A_DDR3_A[15]
A_DDR3_DM2
A_DDR3_A[12]
A_DDR3_A[5]
A_DDR3_A[6]
A_DDR3_A[7]
R13134 240
1%
120Hz
A_DDR3_A[4]
A_DDR3_A[2]
A_DDR3_MCLKZ
U_MVREFCA_A0
A_DDR3_DQS1B
A_DDR3_A[4]
C13803
1000pF
A_DDR3_A[8]
A_DDR3_DM1
U_MVREFCA_A0
A_DDR3_RASZ
R13122
56
120Hz
A_DDR3_A[10]
A_DDR3_CKE
A_DDR3_A[0]
A-MVREFDQ_U
AR13102
100
100ohm_DDR_VTT
A_DDR3_A[6]
A_DDR3_A[7]
A_DDR3_BA[2]
R13121
1K
1%
120Hz
A_DDR3_A[8]
A_DDR3_BA[1]
R13123
56
120Hz
A_DDR3_A[14]
A_DDR3_A[10]
R13102
1K
OPT
A_DDR3_DQS0
A_DDR3_A[13]
+1.5V_U_DDR
AR13108
100
100ohm_DDR_VTT
A_DDR3_ODT
A_DDR3_A[0]
A_DDR3_A[13]
A_DDR3_A[11]
R1385
1K
1%
OPT
A_DDR3_BA[0]
+1.5V_U_DDR
B-MVREFDQ_U
A_DDR3_CASZ
+1.5V_U_DDR
A_DDR3_ODT
C13222
0.1uF
120Hz
R1383
1K
1%
A_DDR3_A[9]
A_DDR3_BA[1]
+1.5V_U_DDR
C13202
0.1uF
120Hz
+1.5V_U_DDR
A_DDR3_RASZ
A_DDR3_CKE
A_DDR3_DQS1
C13802
0.1uF
OPT
K4B1G1646G-BCMA
IC2700
URSA11_DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A_DDR3_DQS3B
+1.5V_U_DDR
A_DDR3_DQ[16-31]
A_DDR3_CSB2
A_DDR3_A[15]
A_DDR3_A[1]
A_DDR3_BA[0]
R1386
1K
1%
OPT
A_DDR3_MCLK
AR13110
100
100ohm_DDR_VTT
A_DDR3_A[11]
AR13112
100
100ohm_DDR_VTT
A_DDR3_A[14]
U_MVREFCA_A1
A_DDR3_DQS2B
A_DDR3_DM0
C13230
1000pF
120Hz
R13126 240
1%
120Hz
+1.5V_U_DDR
A_DDR3_DQS2
A_DDR3_MCLKZ
A_DDR3_MCLK
+1.5V_U_DDR
A_DDR3_DQ[0-15]
A_DDR3_A[1]
A_DDR3_A[2]
A_DDR3_WEZ
R1384
1K
1%
K4B1G1646G-BCMA
IC2600
URSA11_DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A_DDR3_A[3]
A_DDR3_CKE
DDR_VTT_URSA_1
C13804
1000pF
OPT
A_DDR3_CASZ
R13111
1K
1%
120Hz
A_DDR3_A[14]
A_DDR3_A[9]
A_DDR3_WEZ
AR13106
100
100ohm_DDR_VTT
C13210
1000pF
120Hz
A_DDR3_A[5]
R13110
1K
1%
120Hz
A_DDR3_DQS3
R13120
1K
1%
120Hz
C13233
0.01uF
120Hz
A_DDR3_RESET
A_DDR3_A[12]
U_MVREFCA_A1
A_DDR3_DQS0B
R13112
1K
C13801
0.1uF
A_DDR3_CSB1
+1.5V_U_DDR
A_DDR3_BA[2]
A_DDR3_RESET
NT5CB64M16FP-EK
IC2700-*1
URSA11_DDR_NANYA
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_7
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
NT5CB64M16FP-EK
IC2600-*1
URSA11_DDR_NANYA
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_7
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C13814
0.1uF
120Hz
+1.5V_U_DDR
C13822
0.1uF
120Hz
C13824
0.1uF
120Hz
C13809
0.1uF
120Hz
C13808
0.1uF
120Hz
C13820
0.1uF
120Hz
C13807
0.1uF
120Hz
C13818
0.1uF
120Hz
+1.5V_U_DDR
L13103
BLM18PG121SN1D
120Hz
+1.5V_U_DDR
C13812
0.1uF
120Hz
C13805
0.1uF
120Hz
C13825
0.1uF
120Hz
DDR_VTT_URSA_1
C13823
0.1uF
120Hz
C13806
0.1uF
120Hz
C13158
0.1uF
16V
120Hz
DDR_VTT_URSA
C13132
0.1uF
16V
120Hz
C13813
0.1uF
120Hz
C13821
0.1uF
120Hz
C13174
0.1uF
16V
120Hz
C13106
0.1uF
16V
120Hz
C13816
0.1uF
120Hz
C13112
1uF
10V
120Hz
C13817
0.1uF
120Hz
C13815
0.1uF
120Hz
C13826
0.1uF
120Hz
C13819
0.1uF
120Hz
C13811
0.1uF
120Hz
C13810
0.1uF
120Hz
C136113
0.1uF
16V
120Hz
C136114
0.1uF
16V
120Hz
C136115
0.1uF
16V
120Hz
C136116
0.1uF
16V
120Hz
C136117
0.1uF
16V
120Hz
C136118
0.1uF
16V
120Hz
C136119
0.1uF
16V
120Hz
C136120
0.1uF
16V
120Hz
C136121
0.1uF
16V
120Hz
C136122
0.1uF
16V
120Hz
C136123
0.1uF
16V
120Hz
C136124
0.1uF
16V
120Hz
C136125
0.1uF
16V
120Hz
C136126
0.1uF
16V
120Hz
C136127
0.1uF
16V
120Hz
C136128
0.1uF
16V
120Hz
C136129
0.1uF
16V
120Hz
C136130
0.1uF
16V
120Hz
C136131
0.1uF
16V
120Hz
C136132
0.1uF
16V
120Hz
C136133
0.1uF
16V
120Hz
+1.5V_U_DDR
L
1
3
1
0
4
C
I
S
2
1
J
1
2
1
120Hz
R13101
10K
1/16W
1%
120Hz
C13113
10uF
10V
120Hz
L
1
3
1
0
1
C
I
S
2
1
J
1
2
1
120Hz
C13111
10uF
10V
120Hz
C13118
0.1uF
16V
120Hz
+1.5V_U_DDR +3.3V_U_NORMAL
DDR_VTT_URSA
C13114
10uF
10V
120Hz
IC13101
AP2303MPTR-G1
120Hz
3
VREFEN
2
GND
4
VOUT
1
VIN
5
NC_1
6
VCNTL
7
NC_2
8
NC_3
9
[EP]
C13119
10uF
10V
120Hz
C13110
10uF
10V
120Hz
R13104
10K
1/16W
1%
120Hz
IC119
LGE5352(URSA11)
DRAM_VREF_A
B19
DRAM_ZQ_A
A19
PAD_IO[78]/B-A0/[CD-A0]
E24
PAD_IO[89]/B-A1/[CD-A1]
G27
PAD_IO[80]/B-A2/[CD-A2]
F25
PAD_IO[75]/B-A3/[CD-A3]
G23
PAD_IO[86]/B-A4/[CD-A4]
G26
PAD_IO[74]/B-A5/[CD-A5]
F24
PAD_IO[96]/B-A6/[CD-A6]
G28
PAD_IO[87]/B-A7/[CD-A7]
E27
PAD_IO[92]/B-A8/[CD-A8]
F28
PAD_IO[73]/B-A9/[CD-A9]
D26
PAD_IO[90]/B-A10/[CD-A10]
H26
PAD_IO[83]/B-A11/[CD-A11]
F26
PAD_IO[84]/B-A12/[CD-A12]
H25
PAD_IO[77]/B-A13/[CD-A13]
D27
PAD_IO[82]/B-A14/[CD-A14]
F27
PAD_IO[88]/B-A15/[CD-A15]
J24
PAD_IO[85]/B-BA0/[CD-BA0]
H24
PAD_IO[93]/B-BA1/[CD-BA1]
H27
PAD_IO[81]/B-BA2/[CD-BA2]
G24
PAD_IO[97]/B-RASZ/[CD-RASZ]
K24
PAD_IO[94]/B-CASZ/[CD-CASZ]
K23
PAD_IO[79]/B-WEZ/[CD-WEZ]
H23
PAD_IO[95]/B-ODT/[CD-ODT]
J23
PAD_IO[91]/B-CKE/[CD-CKE]
J27
PAD_IO[76]/B-RST/[CD-RST]
D28
PAD_IO[101]/B-MCLK/[CD-MCLK]
K28
PAD_IO[100]/B-MCLKZ/[CD-MCLKZ]
J26
PAD_IO[99]/B-CSB1/[C-CSB1]
D25
PAD_IO[98]/B-CSB2/[D-CSB2]
C28
PAD_IO[121]/B-DQ[0]/[C-DQL0]
N27
PAD_IO[103]/B-DQ[1]/[C-DQL1]
L26
PAD_IO[120]/B-DQ[2]/[C-DQL2]
N26
PAD_IO[104]/B-DQ[3]/[C-DQL3]
L27
PAD_IO[123]/B-DQ[4]/[C-DQL4]
P26
PAD_IO[102]/B-DQ[5]/[C-DQL5]
K27
PAD_IO[122]/B-DQ[6]/[C-DQL6]
P27
PAD_IO[105]/B-DQ[7]/[C-DQL7]
K26
PAD_IO[110]/B-DQ[8]/[C-DQU0]
L23
PAD_IO[117]/B-DQ[9]/[C-DQU1]
P25
PAD_IO[107]/B-DQ[10]/[C-DQU2]
L24
PAD_IO[119]/B-DQ[11]/[C-DQU3]
P23
PAD_IO[111]/B-DQ[12]/[C-DQU4]
M24
PAD_IO[118]/B-DQ[13]/[C-DQU5]
R24
PAD_IO[109]/B-DQ[14]/[C-DQU6]
L25
PAD_IO[116]/B-DQ[15]/[C-DQU7]
P24
PAD_IO[106]/B-DQM[0]/[C-DML]
M27
PAD_IO[108]/B-DQM[1]/[C-DMU]
N24
PAD_IO[115]/B-DQS[0]/[C-DQSL]
N28
PAD_IO[114]/B-DQSB[0]/[C-DQSLB]
M26
PAD_IO[113]/B-DQS[1]/[C-DQSU]
N23
PAD_IO[112]/B-DQSB[1]/[C-DQSUB]
M23
PAD_IO[143]/B-DQ[16]/[D-DQL0]
V27
PAD_IO[126]/B-DQ[17]/[D-DQL1]
T27
PAD_IO[142]/B-DQ[18]/[D-DQL2]
V26
PAD_IO[127]/B-DQ[19]/[D-DQL3]
T28
PAD_IO[144]/B-DQ[20]/[D-DQL4]
W27
PAD_IO[125]/B-DQ[21]/[D-DQL5]
R27
PAD_IO[145]/B-DQ[22]/[D-DQL6]
W28
PAD_IO[124]/B-DQ[23]/[D-DQL7]
R26
PAD_IO[129]/B-DQ[24]/[D-DQU0]
U24
PAD_IO[141]/B-DQ[25]/[D-DQU1]
W23
PAD_IO[139]_/B-DQ[26]/[D-DQU2]
R23
PAD_IO[138]/B-DQ[27]/[D-DQU3]
W25
NPAD_IO[130]/B-DQ[28]/[D-DQU4]
T24
PAD_IO[133]/B-DQ[29]/[D-DQU5]
W24
PAD_IO[132]/B-DQ[30]/[D-DQU6]
T23
PAD_IO[140]/B-DQ[31]/[D-DQU7]
V23
PAD_IO[128]/B-DQM[2]/[D-DML]
T26
PAD_IO[131]/B-DQM[3]/[D-DMU]
U23
PAD_IO[137]/B-DQS[2]/[D-DQSL]
U26
PAD_IO[136]/B-DQSB[2]/[D-DQSLB]
U27
PAD_IO[135]/B-DQS[3]/[D-DQSU]
V24
PAD_IO[134]/B-DQSB[3]/[D-DQSUB]
U25
DRAM_VREF_B
B25
DRAM_ZQ_B
A25
R136002 10K
1/16W 1%
AR13100-*1
56
56ohm_DDR_VTT
AR13102-*1
56
56ohm_DDR_VTT
AR13104-*1
56
56ohm_DDR_VTT
AR13106-*1
56
56ohm_DDR_VTT
AR13108-*1
56
56ohm_DDR_VTT
AR13110-*1
56
56ohm_DDR_VTT
AR13112-*1
56
56ohm_DDR_VTT
AR13100
100
100ohm_DDR_VTT
DDR PHY VREF
Close to DDR POWER PIN
Decap removed
Close to DDR POWER PIN
Close to DDR POWER PIN
Close to DDR POWER PIN
* DDR_VTT
Copyright © 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only