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Copyright ©
LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
Main IC
eMMC (4GB)
USB1 (2
.0)
OCP
USB2 (2
.0)
HDMI
3
HDMI
2(ARC)
HDMI
1
Air
/
Cable
TUNER
CVBS
SIF
MI
COM
IR
/ KEY
USB_WI
FI
X_
TAL
27MHz
Sub Assy
LAN
ETHERNET
SPDIF
AV/COMP
CVBS/YPbPr
SPDIF OUT
MA
IN
Audio
AM
P
I2S
Out
I2
C
4
Vx
1 51P
(8 lane)
Vx
1
/ EPI
/ CEDS
FCIC
SP
I/
I2C
6
Ma
in
PM
IC
M0
M1
IF
CVBS
/SIF
GST/
MC
LK/GCLK/EO
/I2C
6
NVRAM
(256Kb)
I2
C_1
I2
C 2
EPI/CEDS
bloc
k
TS
DDR3
2133
X
32
(256
MB
X
2EA)
DDR3
2133
X
32
(512M
B
X
2EA)
EPI
60P
(65”:8 lane,
55”
↓:6
lane),
CEDS 68
P
IR
/KEY
I2
C_SDA_1
1.5V
DDR
0.95V
Core&CPU
3.3V
Norm
al
1.0V
Eth
3.5V
ST_BY
1.8V
5V
Norm
al
Sub PM
IC
0.
95
V
1.
5V
3.
3V
5V
1V
1.
8V
3.
5V
_S
T
0.
95
V
1.
5V
3.
3V
3.
3V
5V
1V
1.
8V
1.
8V
3.
5V
_S
T
3.
5V
_S
T
3.
3V
3.
5V
_S
T
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
3V
13
V
13
V
3.
3V
13
V(
PA
NE
L_
VC
C)
13
V(
PA
NE
L_
VC
C)
To
Pa
ne
l
From
Power B/D
13
V
To
W
IF
I/B
T
Co
m
bo
IF+/-
Ga
mma
IC
3.
3V
Signal Flow
Supply Power
Input/Output Power
Summary of Contents for 65UM6900PUA
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