THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
15/01/21
A_DDR3_DQ[0]
A_DDR3_DQ[1]
A_DDR3_DQ[2]
A_DDR3_DQ[3]
A_DDR3_DQ[4]
A_DDR3_DQ[5]
A_DDR3_DQ[6]
A_DDR3_DQ[7]
A_DDR3_DQ[8]
A_DDR3_DQ[9]
A_DDR3_DQ[10]
A_DDR3_DQ[11]
A_DDR3_DQ[12]
A_DDR3_DQ[13]
A_DDR3_DQ[14]
A_DDR3_DQ[15]
A_DDR3_DQ[16]
A_DDR3_DQ[17]
A_DDR3_DQ[18]
A_DDR3_DQ[19]
A_DDR3_DQ[20]
A_DDR3_DQ[21]
A_DDR3_DQ[22]
A_DDR3_DQ[23]
A_DDR3_DQ[24]
A_DDR3_DQ[25]
A_DDR3_DQ[26]
A_DDR3_DQ[27]
A_DDR3_DQ[28]
A_DDR3_DQ[29]
A_DDR3_DQ[30]
A_DDR3_DQ[31]
C13014
10uF
10V
A_DDR3_DQ[16-31]
A_DDR3_RESET
A_DDR3_A[14]
C13024
0.1uF
16V
A_DDR3_DQS0B
A_DDR3_A[9]
A_DDR3_A[1]
A_DDR3_CASZ
A_DDR3_BA[1]
C13032
0.1uF
16V
K4B1G1646G-BCMA
IC13002
URSA11_DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A_DDR3_A[12]
A_DDR3_A[1]
A_DDR3_RASZ
C13017
0.1uF
A_DDR3_A[10]
C13061
1000pF
C13029
0.1uF
R13002
100K
1%
A_DDR3_BA[0]
A_DDR3_CKE
K4B1G1646G-BCMA
IC13001
URSA11_DDR_SAMSUNG
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C13016
0.1uF
C13033
0.1uF
A_DDR3_MCLKZ
A_DDR3_DQ[0-15]
A_DDR3_A[15]
A_DDR3_DQS0
U_MVREFCA_A0
C13028
0.1uF
16V
C13005
0.1uF
+1.5V_U_DDR
A_DDR3_CKE
C13026
0.1uF
A_DDR3_A[3]
A_DDR3_BA[0]
L13002
BLM18PG121SN1D
A_DDR3_DQS1
C13036
0.1uF
A_DDR3_RESET
C13010
0.1uF
C13047
0.1uF
16V
R13012
1K
1%
A_DDR3_A[14]
A_DDR3_WEZ
+1.5V_U_DDR
C13051
0.1uF
16V
DDR_VTT_URSA
C13045
0.1uF
16V
C13055
0.1uF
A_DDR3_DQS3B
DDR_VTT_URSA
C13018
0.1uF
16V
DDR_VTT_URSA_1
A_DDR3_A[6]
A_DDR3_CKE
A_DDR3_DM2
A_DDR3_DM3
A_DDR3_A[8]
A_DDR3_RASZ
C13050
0.1uF
16V
C13000
0.1uF
C13040
0.1uF
16V
A_DDR3_RESET
A_DDR3_A[9]
A_DDR3_A[5]
A_DDR3_A[10]
C13031
0.1uF
16V
A_DDR3_A[8]
R13011
1K
R13016
240
1%
C13035
0.1uF
16V
C13052
0.1uF
16V
C13048
0.1uF
16V
C13025
0.1uF
C13039
10uF
10V
A_DDR3_A[0]
A_DDR3_A[15]
A_DDR3_DM1
C13013
0.1uF
16V
R13014
56
C13002
0.1uF
16V
C13027
0.1uF
+1.5V_U_DDR
A_DDR3_MCLK
C13056
0.1uF
16V
+1.5V_U_DDR
A_DDR3_A[13]
+1.5V_U_DDR
C13001
0.1uF
A_DDR3_CASZ
R13015
56
NT5CB64M16FP-EK
IC13002-*1
URSA11_DDR_NANYA
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_7
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
A_DDR3_DQS1B
C13008
0.1uF
16V
A_DDR3_MCLKZ
A_DDR3_A[12]
A_DDR3_A[0]
C13062
0.01uF
A_DDR3_A[2]
U_MVREFCA_A1
C13042
0.1uF
16V
+1.5V_U_DDR
+1.5V_U_DDR
A_DDR3_WEZ
C13043
0.1uF
16V
+1.5V_U_DDR
A_DDR3_DQS2B
R13004
1K
OPT
A_DDR3_A[4]
A_DDR3_A[4]
A_DDR3_DQS3
C13020 0.1uF
16V
A_DDR3_BA[2]
C13007
0.1uF
R13010
1K
1%
C13019
10uF
10V
C13015
0.1uF
+1.5V_U_DDR
+1.5V_U_DDR
A_DDR3_A[6]
R13017
240
1%
A_DDR3_A[14]
C13021
0.1uF
L13001
CIS21J121
U_MVREFCA_A0
C13030
0.1uF
A_DDR3_A[3]
+1.5V_U_DDR
A_DDR3_A[7]
C13006
0.1uF
A_DDR3_BA[2]
A_DDR3_A[7]
C13041
0.1uF
16V
R13001
100K
1%
L13000
CIS21J121
C13059
1000pF
IC13000
AP2303MPTR-G1
3
VREFEN
2
GND
4
VOUT
1
VIN
5
NC_1
6
VCNTL
7
NC_2
8
NC_3
9
[EP]
C13023
0.1uF
C13046
0.1uF
16V
+1.5V_U_DDR
A_DDR3_DQS2
C13022
0.1uF
A_DDR3_A[11]
C13034
0.1uF
16V
C13009
10uF
10V
C13044
0.1uF
16V
R13013
1K
1%
A_DDR3_CSB2
C13003
0.1uF
A_DDR3_BA[1]
A_DDR3_ODT
C13049
1uF
10V
A_DDR3_ODT
C13037
0.1uF
16V
C13060
0.1uF
C13038
0.1uF
16V
DDR_VTT_URSA_1
A_DDR3_CSB1
A_DDR3_A[13]
A_DDR3_A[2]
U_MVREFCA_A1
A_DDR3_A[11]
R13009
1K
1%
NT5CB64M16FP-EK
IC13001-*1
URSA11_DDR_NANYA
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_6
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_7
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
+3.3V_NORMAL
C13011
0.1uF
C13012
0.1uF
C13004
10uF
10V
A_DDR3_DM0
A_DDR3_A[5]
A_DDR3_MCLK
R14200
10K
1/16W
1%
AR13000
56
AR13001
56
AR13002
56
AR13003
56
AR13004
56
AR13005
56
AR13006
56
TXDBN5_L_URSA11
TXDBN4_L_URSA11
TXDBP1_L
C12839
0.1uF
C12837
0.1uF
TXDBP4_L
C12840
0.1uF
TXDBP3_L_URSA11
C12836
0.1uF
TXDBN7_L_URSA11
TXDBN0_L_URSA11
TXDBN2_L
C12847
0.1uF
TXDBP3_L
C12843
0.1uF
C12832
0.1uF
TXDBN2_L_URSA11
C12833
0.1uF
TXDBP7_L_URSA11
TXDBN3_L_URSA11
TXDBP2_L
TXDBN6_L
C12835
0.1uF
C12841
0.1uF
TXDBN4_L
TXDBP6_L_URSA11
C12846
0.1uF
TXDBP1_L_URSA11
TXDBP2_L_URSA11
TXDBP5_L
TXDBN5_L
TXDBP7_L
C12838
0.1uF
C12842
0.1uF
TXDBN6_L_URSA11
C12845
0.1uF
TXDBN1_L_URSA11
C12834
0.1uF
TXDBP5_L_URSA11
C12844
0.1uF
TXDBN0_L
TXDBP0_L
TXDBN3_L
TXDBP4_L_URSA11
TXDBN7_L
TXDBP6_L
TXDBP0_L_URSA11
TXDBN1_L
URSA11_DDR
Close to DDR POWER PIN
Close to DDR POWER PIN
DDR PHY VREF
Close to DDR POWER PIN
Decap removed
Close to DDR POWER PIN
* DDR_VTT
BSD-15Y-LM14A-143_00-HD
UF77 ONLY
For 120Hz Vb1
Copyright © 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 65EF9500
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