U14 Block Diagram (Internal)
R
3
Digital die
DDR I/F(32bitx1)
800MHz
DD
R
76
• MCU
9
Tensilica’s 108mini
H13D
2
I2C(S)
Tensilica
108m@198MHz
Super Resolution
4
• Memory
9
Unified memory architecture
9
DDR3-1600MHz 32bit
• Interface
H13D
108m@198MHz
ROM 8KB
I$16KB D$8KB
IRAM128KB DRAM128KB
Super-Resolution
FHD
Æ
3840x2160
4K@60P PQ
Sharpness/Color/Contrast
SPI(S)
4
H13D
(GPIO)
Reset
1
HS LVDS Rx
24
H13D
Combo Tx
HS LVDS 4-link
Vx1 8-lane
Combo Tx
HS LVDS 2 li k
24
48
Interface
9
Input
: HS-LVDS 4-link (2+2)
: HDMI1.4 2-port
9
Output
14
4K 2D-to-3D
Sharpness/Color/Contrast
UGM/Local Dimming
Gamma/WB
2
I2C(M/S)
HDMI Switch
HDMI Rx
1.4b
14
HDMI Switch
24
HS LVDS Rx
2-link
H13D
2-link
HS LVDS 2-link
Vx1 4-lane
: HS-LVDS 6-link (4+2)
: Vx1 12-lane (8+4)
• PKG
9
23X23 FcBGA
S i l Fl h
8
GPIO
HDMI Rx
1.4b
JTAG Ready
JTAG
5
4
(
)
HDMI Switch
Separate OSD
Serial Flash
RS-232C
2
SPI(M)
CLK
UART
TEST
Boot Mode
Crystal
2
4
2
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Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 55UB8500
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