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Copyright ©
LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
1. Main IC
MA
IN
Audio
AM
P
I2C
OPTIC
LAN
HDMI
1 HDMI 2.0
EEPROM
(NVRAM)
(256Kb)
PHY3_R
X0
N
Antenna (UHDTV)
Antenna /C
able
USB1 (2
.0)
eMMC
(4GB)
Mi
co
m
X_
TAL
24MHz
NT
SC
/ATS
C3
.0
X_
TAL
32.768KHz
I2
C 4
R E A R
SPDIF
OUT
ETHERNET
I2
C 1
SUB ASSY
IR
/ KEY
ST-BY
LED
WI
FI/BT
Co
mb
o
USB_
WI
FI
CVBS
/ SIF
HDMI
3 HDMI 2.0
US
B2
(2.0)
HDMI
2(ARC)
HDMI
2.0
DATA
/ CL
K
US
B3_0
USB2_2
PHY2_R
X0
N
PHY1_R
X0
N
I2
C6
HDMI
4 HDMI 2.0
PHY0_R
X0
N
PM
IC
Sub PM
IC
DDR4
2666
512MB / 1G
B
DDR4
2666
512MB / 1GB
DDR3 2133
512MB
DDR3
/ 2133
512MB
USB3 (2
.0)
USB2_1
Side
Rear
TU670
1
IF
X101
I2
C
0
Sub Audio AM
P
I2
C 5
Side
Rear
IC
400
IC401
IC501
IC502
IC
102
IC
8800
IC8000
IC8100
I2
C
0
I2S
I2S
IC
5300
IC
5400
IC
3000
X300
1
JK4200
JK4400
JK4600
JK3101
JK3102
JK3103
JK3104
TS
Ma
in
IC
Summary of Contents for 55SK8550PUA
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