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2. H13 Block Diagram (Internal)
Digital Chip Total Pin : 491w/o Power
Tuner
DIF
TS (P)
System
Demux
Global Baseband
V/Q, DVB-T/C ISDB-T
H13A
H13D
Video Decoder
Multi-STD
HD Decoder
2D GFX
UARTx3
TS(P)
TS(P)
GBB AFE
1ch@30MHz
w/ PLL
DVB-CI/CI+
Analog Chip Total Pin : 183w/o Power
Digital Chip Total Pin : 491w/o Power
AtoDPin : 79
TS(S)
GPU Rogue Han
USB2.0x3
GPIO 136
TS(S)
SDRAM
(MCP)
Tuner
Audio DSP
Multi-STD
Audio Decoder
LX4 HiFi EP
SIF
AAD
(THAT)
Mu
x
S
W
I2S(External)
(Boda950)
Audio
JPG/PNG Decoder
TrustZone
So nd DSP
JPG Encoder
EMAC
SCI
SPIx2
I2Cx10
PHY
BTSC AFE
w/ PLL
1ch L/R
Audio-ADC
Video Encoder
1080p@30fps
USB3.0 x1
GPIOx136
I2S
S
Audio DAC (48KHz)
CPU
ARMCA9 Core
Dual 1.2GHz
32KBI$
32KBD$
1MB L2 $
Sound DSP
Clear Voice II
Perceptual
Volume Control
Slim SPK
DivX
Digital AMP
I2S
I2S(HPD)
CPU
64KB SRAM
48KB ROM
UART
OTP
Timer
eMMC
DMAC(8ch)
Timer
WDT
SRAM 16KB
Digital
Audio
24b@48KHz
Secure Engine
Audio DAC
(48KHz )
I2S
SW
CVBS(3ch)
CVBS AFE(2-ch)
12b@54MHz
CVBS-Out
DE
CVBS
Encoder
1MB L2 $
SW
3 h Vid
Bluetooth
SPDIF
CVD
Y/C
CVBS
Timer
BE
Audio
Output
MCU
CVBS DAC
5x1ch (1ch)
ux
D
S Combo
H
z)
MCU
Component(2ch)
Mux
10x3ch
LVDS
Tx
Audio PLL
w/ DCO
Source Mux
TN
R
De-interlacer
Main/Sub Scaler
H3D
VCR
SW
3ch Video
AFE
w/ LLPLL
LVDS
Rx
I2Cx1
H3D
FRC
SRE
PE1
OSD
LED
Output formatter
TC
O
N
Capture
Block
(3CH)
I2Cx1
HDMI
(1-Link)
HDMI
M
u
Vx
1/EPI/LV
D
(120
H
CPLL
DCO
x2
GPIOIx16
HDMI-Rx 1.4
(1-port PHY)
3D, ARC, 4kx2k
DDR3 PHY
DDR3 Controller
DDR3 PHY
DDR3 Controller
SPLL
DDR
PLL
DPLL
DDR
PLL
16
16
I2Cx1
HDMI
16
16
GPIOIx16
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Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 55EA970T
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