- 12 -
Copyright ©
LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
1. Main IC
Ma
in IC
eMMC
(4
GB
)
USB1
(2
.0)
OC
P
USB2
(2
.0)
HD
MI
3
HD
MI2(
AR
C)
HD
MI
1
Ai
r /
Cabl
e
TU
NE
R
CV
BS
SI
F
MI
CO
M
IR
/ KE
Y
USB_
WIFI
X_
TA
L
27M
Hz
Sub Assy
LA
N
ETHE
RNET
SPDIF
AV/C
OMP
CVBS/
YPbPr
SPDI
F OU
T
MA
IN
Au
di
o AM
P
I2S
Ou
t
I2C
4
Vx
1 51P
(8
la
ne
)
Vx
1 /
EP
I/
CE
DS
FCIC
SP
I/
I2
C
6
Ma
in
PM
IC
M0
M1
IF
CVBS
/S
IF
GS
T/
MC
LK
/G
CL
K/
EO
/I2
C
6
NV
RA
M
(2
56K
b)
I2C_
1
I2C
2
EP
I/C
ED
S bl
oc
k
TS
DDR3
2133
X
32
(256M
B
X
2EA)
DDR3
2133
X
32
(512M
B
X
2EA)
EP
I 60P
(65”
:8
lane
, 55”
↓:6l
an
e)
, CE
DS
68P
IR/
KEY
I2C_
SD
A_
1
1.5V DD
R
0.95V
Co
re
&C
PU
3.3V No
rm
al
1.0V Et
h
3.5V ST
_B
Y
1.8V
5V
No
rm
al
Su
b
PM
IC
0.
95
V
1.
5V
3.
3V
5V
1V
1.
8V
3.
5V
_S
T
0.
95
V
1.
5V
3.
3V
3.
3V
5V
1V
1.
8V
1.
8V
3.
5V
_S
T
3.
5V
_S
T
3.
3V
3.
5V
_S
T
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
5V
_S
T
13
V
3.
3V
13
V
13
V
3.
3V
13
V(
PA
NE
L_
VC
C)
13
V(
PA
NE
L_
VC
C)
To
Pa
ne
l
Fr
om
Po
we
r
B/
D
13
V
To
W
IF
I/B
T
Co
m
bo
IF
+/-
Ga
mm
a
IC
3.
3V
Signal Flow
Supply Power
Input/Output Power