THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M0_DDR_DQ19
M0_DDR_DQ1
M0_DDR_DQS2
R402
1K
1%
M0_DDR_A9
M0_1_DDR_VREFCA
M0_DDR_DQS_N1
M0_DDR_DQS1
M0_DDR_DQ1
R415
1K
1%
VREF_M0_0
M0_DDR_DQ10
R411
1K
1%
M0_DDR_DQ25
M0_DDR_A15
M0_DDR_WEN
R408
1K
1%
M0_DDR_DQ8
M0_DDR_A7
M0_DDR_DQS_N0
M0_1_DDR_VREFDQ
M0_DDR_A6
M0_DDR_DQ15
M0_DDR_A13
M0_DDR_DQS_N2
C401
0.1uF
M0_DDR_DQ4
M0_DDR_A11
M0_DDR_DQS1
M0_DDR_DQ26
M0_DDR_DQ21
M0_DDR_A5
+1.5V_DDR
R
4
1
0
1
0
0
M0_DDR_BA0
M0_D_CLKN
M0_DDR_DQ16
M0_DDR_DQ13
M0_DDR_A8
M0_DDR_A10
M0_DDR_DQ21
R412
1K
1%
M0_DDR_DM1
M0_DDR_DQ25
+1.5V_DDR
M0_U_CLKN
M0_DDR_DQS0
M0_DDR_A4
M0_D_CLK
M0_DDR_A13
M0_DDR_A9
M0_D_CLK
M0_DDR_DQ17
M0_DDR_DQS3
M0_DDR_A6
M0_DDR_VREFDQ
M0_DDR_A14
M0_DDR_DQ12
M0_D_CLKN
M0_DDR_DQ23
H5TQ4G63AFR-PBC
IC402
DDR_512MB_HYNIX_1600_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_BA0
M0_DDR_A5
M0_DDR_BA2
M0_DDR_DQS_N3
M0_DDR_A1
M0_DDR_BA2
M0_DDR_DQ11
M0_DDR_DQ27
M0_DDR_DQS0
M0_DDR_DQ17
VREF_M0_1
R416
1K
1%
M0_DDR_DQ3
M0_DDR_A3
M0_DDR_A2
M0_DDR_A14
M0_DDR_CKE
M0_DDR_CASN
C407
0.1uF
M0_DDR_A4
R419
240
1%
M0_DDR_DQ24
M0_DDR_CKE
M0_DDR_A13
M0_DDR_DQ7
M0_DDR_DQ9
M0_DDR_DM1
M0_DDR_DQ9
M0_DDR_DQ13
M0_DDR_A12
+1.5V_DDR
C406
0.1uF
M0_U_CLK
M0_DDR_WEN
R414
1K
1%
M0_DDR_DQS_N2
VREF_M0_1
M0_1_DDR_VREFCA
M0_DDR_BA1
C408
0.1uF
M0_DDR_CKE
M0_DDR_DQ20
M0_DDR_DQ5
M0_DDR_A1
R404
10K
OPT
M0_U_CLKN
M0_DDR_DM2
M0_DDR_BA2
M0_DDR_DQS2
M0_DDR_DQ31
M0_DDR_DQ11
M0_DDR_DQ30
R409
1K
1%
M0_DDR_DQ15
M0_DDR_A14
M0_DDR_BA1
M0_DDR_DQS_N3
M0_DDR_A15
M0_DDR_DQ5
M0_DDR_A8
M0_DDR_DQ30
M0_DDR_A6
M0_DDR_DQS_N1
M0_DDR_DQ6
R403
1K
1%
M0_DDR_ODT
M0_DDR_A10
C403
0.1uF
C402
0.1uF
MT41K256M16HA-125:E
IC402-*1
DDR_512MB_MICRON
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_A3
M0_DDR_DQ27
+1.5V_DDR
M0_DDR_DQ3
M0_DDR_A12
C430
1uF
M0_DDR_DQ19
M0_DDR_DQ8
M0_DDR_BA0
M0_DDR_DQ26
R401
240
1%
M0_DDR_DQ22
M0_DDR_DQS3
M0_DDR_ODT
M0_DDR_A15
M0_D_CLKN
+1.5V_DDR
M0_DDR_RESET_N
C414
1uF
M0_DDR_DQ7
M0_DDR_DQ14
R406
1K
1%
M0_DDR_DM0
M0_DDR_BA1
M0_DDR_RASN
M0_DDR_DQ14
M0_DDR_DQ12
M0_U_CLKN
MT41K256M16HA-125:E
IC401-*1
DDR_512MB_MICRON
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_DDR_CASN
M0_DDR_A2
M0_DDR_CKE
M0_DDR_DQ0
M0_DDR_CASN
M0_DDR_A9
M0_DDR_RESET_N
M0_DDR_DM0
M0_DDR_A11
M0_DDR_A0
M0_DDR_A11
M0_DDR_DQ29
M0_DDR_A7
M0_DDR_DQ6
C429
1uF
R418
240
1%
M0_DDR_A10
+1.5V_DDR
M0_DDR_A5
M0_DDR_RASN
M0_DDR_DM2
M0_DDR_DM3
M0_D_CLK
M0_DDR_DQ29
M0_DDR_DQ18
M0_DDR_DQ31
M0_DDR_DQ10
R
4
0
5
1
0
0
M0_DDR_DQ2
M0_DDR_A8
M0_DDR_RASN
M0_DDR_A4
M0_DDR_DQS_N0
M0_DDR_DQ22
VREF_M0_0
M0_DDR_RESET_N
M0_DDR_DQ16
M0_DDR_DQ20
M0_DDR_DQ0
+1.5V_DDR
M0_DDR_A3
M0_DDR_DQ2
M0_DDR_DQ23
M0_1_DDR_VREFDQ
M0_DDR_DQ24
M0_DDR_A2
M0_DDR_A0
R417
10K
H5TQ4G63AFR-PBC
IC401
DDR_512MB_HYNIX_1600_29n
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
A14
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
M0_U_CLK
M0_U_CLK
M0_DDR_DQ18
M0_DDR_VREFDQ
R407
1K
1%
M0_DDR_DQ28
C413
1uF
M0_DDR_RESET_N
M0_DDR_DM3
M0_DDR_WEN
M0_DDR_ODT
+1.5V_DDR
M0_DDR_VREFCA
M0_DDR_A0
M0_DDR_A1
M0_DDR_VREFCA
M0_DDR_DQ28
R413
1K
1%
M0_DDR_DQ4
M0_DDR_A7
+1.5V_DDR
M0_DDR_A12
IC101
LG1311
M0_DDR_VREF1
A22
M0_DDR_VREF2
A3
M0_DDR_A0
E13
M0_DDR_A1
E11
M0_DDR_A2
E15
M0_DDR_A3
E17
M0_DDR_A4
D8
M0_DDR_A5
D16
M0_DDR_A6
D9
M0_DDR_A7
E16
M0_DDR_A8
E9
M0_DDR_A9
E14
M0_DDR_A10
D7
M0_DDR_A11
D10
M0_DDR_A12
D11
M0_DDR_A13
D14
M0_DDR_A14
E10
M0_DDR_A15
E12
M0_DDR_BA0
D17
M0_DDR_BA1
E8
M0_DDR_BA2
D13
M0_DDR_U_CLKP
C8
M0_DDR_U_CLKN
B8
M0_DDR_D_CLKP
C17
M0_DDR_D_CLKN
B17
M0_DDR_CKE
D12
M0_DDR_ODT
E19
M0_DDR_RASN
D19
M0_DDR_CASN
D18
M0_DDR_WEN
E18
M0_DDR_RESET_N
D15
M0_DDR_DQS_P0
B18
M0_DDR_DQS_N0
C18
M0_DDR_DQS_P1
B16
M0_DDR_DQS_N1
A16
M0_DDR_DQS_P2
B9
M0_DDR_DQS_N2
C9
M0_DDR_DQS_P3
B7
M0_DDR_DQS_N3
A7
M0_DDR_DM0
A15
M0_DDR_DM1
A18
M0_DDR_DM2
A6
M0_DDR_DM3
A9
M0_DDR_DQ0
B20
M0_DDR_DQ1
B13
M0_DDR_DQ2
C21
M0_DDR_DQ3
C14
M0_DDR_DQ4
A21
M0_DDR_DQ5
A13
M0_DDR_DQ6
B21
M0_DDR_DQ7
C13
M0_DDR_DQ8
B14
M0_DDR_DQ9
B19
M0_DDR_DQ10
C15
M0_DDR_DQ11
C20
M0_DDR_DQ12
C16
M0_DDR_DQ13
A19
M0_DDR_DQ14
B15
M0_DDR_DQ15
C19
M0_DDR_DQ16
B11
M0_DDR_DQ17
C5
M0_DDR_DQ18
C12
M0_DDR_DQ19
B4
M0_DDR_DQ20
A12
M0_DDR_DQ21
A4
M0_DDR_DQ22
B12
M0_DDR_DQ23
C4
M0_DDR_DQ24
B5
M0_DDR_DQ25
B10
M0_DDR_DQ26
C6
M0_DDR_DQ27
C11
M0_DDR_DQ28
C7
M0_DDR_DQ29
A10
M0_DDR_DQ30
B6
M0_DDR_DQ31
C10
M0_DDR_ZQCAL
E7
MID_LG1311
4
2013.04.04
M14 DDR3-M0
31
DDR3
4Gbit
(x16)
DDR3
4Gbit
(x16)
PAGE 4
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 50LB6500
Page 50: ......
