Jack Interface
[VI_SC_R1],[VI_SC_G1],[VI_SC_B1]
BCM35230
[COMP1_DET]
[COMP1_Y]
[COMP1_Pb]
[COMP1_Pr]
DSUB_R / G / B
PC L,R
EDID EEPROM
AT24C02BN-10SU-1.8
RGB DET
[/G+/B+]
DSUB_ V / HSYNC
[DSUB_V/H SYNC]
[DSUB_DET] // GPIO
[EDID_WP]
MICOM
[RGB_DDC_SCL]
[RGB_DDC_SDA]
RGB_DDC_SCL
RGB_DDC_SDA
[PC_L_IN]
[PC_R_IN]
[SPDIF_OUT]
SPDIF
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
COMP_Y
COMP_PB
COMP_PR
COMP DET
COMP1
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
AV1
AV2
COMP2 OPT
COMP2_R/G/B
0 OH
M
[BSC_S_SCL]
[BSC_S_SDA]
Copyright ⓒ 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 47LV3700
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