THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
M14-Peripheral
EB_ADDR[4]
EMMC_DATA[0]
EB_ADDR[1]
EB_DATA[2]
EB_ADDR[3]
EMMC_DATA[2]
EB_ADDR[10]
EB_DATA[0]
EMMC_DATA[7]
EMMC_DATA[4]
EB_ADDR[13]
EB_ADDR[6]
EMMC_DATA[3]
EB_ADDR[0]
EB_ADDR[2]
EB_DATA[3]
EMMC_DATA[1]
EB_ADDR[8]
EMMC_DATA[6]
EB_ADDR[5]
EB_DATA[6]
EB_DATA[4]
EB_ADDR[9]
EB_ADDR[7]
EB_DATA[7]
EB_DATA[5]
EB_ADDR[12]
EB_ADDR[14]
EB_DATA[1]
EMMC_DATA[5]
EB_ADDR[11]
OPM1
CAM_INPACK_N
C101-*1
6.8pF
50V
LOADCAP_DVB_PCB
IRB_SPI_MISO/TDI1
C107
0.1uF
16V
R159
3.3K
TP111
I2C_SCL4
TRST_N1
USB_DP3
R101
3.3K
OPT
R156
1.2K
KR_PIP_NOT
TDI0
USB_DM1
SOC_RESET
USB_DP1
I2C_SCL2
LED_SDA
EB_ADDR[0-14]
/PCM_CE1
C102-*1
6.8pF
50V
LOADCAP_DVB_PCB
CAM_IREQ_N
PLLSET1
XTAL_IN
XTAL_IN
R104
3.3K
OPT
TRST_N1
R162
3.3K
OPM0
LED_SCL
R155-*1
3.3K
KR_PIP
I2C_SCL5
R108
33
I2C_SDA6
USB_CTL2
USB_CTL3
I2C_SDA2
EB_WE_N
R158
3.3K
R163
10K
OPT
EB_BE_N1
R182
10K
OPT
R161
3.3K
I2C_SCL4
R105
3.3K
OPT
TP113
IRB_SPI_MISO/TDI1
I2C_SDA1
IRB_SPI_MOSI/TDO1
XTAL_OUT
USB_CTL1
C104
0.1uF
16V
I2C_SDA6
I2C_SDA5
+3.3V_NORMAL
I2C_SDA5
R149
3.3K
TP116
EB_WE_N
I2C_SDA_MICOM_SOC
P102
12507WS-04L
OPT
1
2
3
4
5
I2C_SCL5
R183
10K
I2C_SDA1
PCM_RESET
INSTANT_BOOT
R148-*1
1.5K
KR_PIP
SOC_RESET
USB_DP2
EB_BE_N1
R102
3.3K
OPT
P104
12505WS-10A00
OPT
1
2
3
4
5
6
7
8
9
10
11
PLLSET0
/PCM_CE2
CAM_WAIT_N
PCM_5V_CTL
PLLSET0
I2C_SCL_MICOM_SOC
/PCM_CE1
I2C_SCL6
R184
10K
IRB_SPI_MOSI/TDO1
EB_DATA[0-7]
+3.3V_NORMAL
CAM_CD2_N
EB_BE_N0
TP108
OPM0
R157
3.3K
SOC_TX
+3.3V_NORMAL
R107
33
EB_OE_N
WIFI_DP
R179
10K
1/16W
5%
I2C_SCL2
EB_BE_N0
/USB_OCD3
/USB_OCD2
IRB_SPI_CK/TCK1
EMMC_DATA[0-7]
R185
10K
L/DIM0_VS (TRST0_N)
CAM_CD2_N
I2C_SDA4
I2C_SDA5
IRB_SPI_SS/TMS1
R171
200
1%
R150
3.3K
PWM_DIM2
I2C_SDA_MICOM_SOC
+3.3V_NORMAL
I2C_SDA4
R178
33
R106
3.3K
OPT
CAM_REG_N
TP115
TP106
CAM_REG_N
R118
1M
FORCED_JTAG_0
TP110
BOOT_MODE
TCK0
I2C_SCL_MICOM_SOC
PLLSET1
CAM_CD1_N
TP109
EB_ADDR[0-14]
+3.3V_NORMAL
M_REMOTE_TX
I2C_SCL1
L/DIM0_SCLK
TP114
EMMC_CLK
R148
3.3K
KR_PIP_NOT
P103
12505WS-10A00
JTAG_CPU
1
2
3
4
5
6
7
8
9
10
11
R146
3.3K
KR_PIP_NOT
TP103
R143
33
FORCED_JTAG_0
XTAL_OUT
R172
200
1%
I2C_SCL1
R160
3.3K
TP105
PCM_RESET
USB_DM3
R156-*1
3.3K
KR_PIP
AR101
33
R103
3.3K
OPT
L/DIM0_SCLK (TMS0)
R121
3.3K
OPT
+3.3V_NORMAL
R180
560
USB_DM2
+3.3V_NORMAL
R128
3.3K
CAM_CD1_N
EB_OE_N
+3.3V_NORMAL
CAM_INPACK_N
PCM_5V_CTL
R169
33
+3.3V_NORMAL
+3.3V_NORMAL
I2C_SCL5
WIFI_DM
IRB_SPI_SS/TMS1
IRB_SPI_CK/TCK1
I2C_SCL6
PWM_DIM
TP102
IC103
AT24C256C-SSHL-T
NVRAM_ATMEL
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
CAM_IREQ_N
TP107
SOC_RESET
/USB_OCD1
EB_DATA[0-7]
TP117
R146-*1
1.5K
KR_PIP
M_REMOTE_RX
TDI0
CAM_WAIT_N
BOOT_MODE
TP112
EMMC_CMD
R144
33
R155
1.2K
KR_PIP_NOT
L/DIM0_MOSI (TDO0)
EMMC_RST
IC103-*1
M24256-BRMN6TP
NVRAM_ST
3
E2
2
E1
4
VSS
1
E0
5
SDA
6
SCL
7
WC
8
VCC
L/DIM0_VS
L/DIM0_MOSI
TP104
/PCM_CE2
TCK0
R127
3.3K
OPT
I2C_SDA2
+3.3V_TUNER
R174
200
1%
+3.3V_TUNER
R173
200
1%
OPM1
X101
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
SOC_RX
AR100
33
1/16W
IC101
LG1311
XIN_MAIN
B23
XO_MAIN
A23
PORES_N
AG21
BOOT_MODE
AJ18
PLLSET0
AB8
PLLSET1
AC8
OPM0
AD8
OPM1
AE8
L_VSOUT_LD/TRST0_N
Y7
DIM0_SCLK/TMS0
Y6
DIM1_SCLK/TCK0
W7
DIM1_MOSI/TDI0
W6
DIM0_MOSI/TDO0
W5
SPI_CS0
AG30
SPI_SCLK0
AG28
SPI_DO0
AG29
SPI_DI0/TRST1_N
AH29
SPI_CS1/TMS1
AJ27
SPI_SCLK1/TCK1
AH27
SPI_DO1/TDO1
AG26
SPI_DI1/TDI1
AH26
EXT_INTR0
AJ12
EXT_INTR1
AJ13
EXT_INTR2
AH12
EXT_INTR3
AG12
UART0_RXD
AH23
UART0_TXD
AG22
UART1_RXD
AH7
UART1_TXD
AJ7
UART1_RTS_N
AG8
UART1_CTS_N
AH8
SCL0
AH11
SDA0
AG11
SCL1
AH9
SDA1
AG9
SCL2
AG10
SDA2
AJ9
SCL3
AH22
SDA3
AJ22
SCL4
AH10
SDA4
AJ10
SCL5
AG23
SDA5
AH24
PWM0
AC6
PWM1
AC7
PWM2
AD7
PWM_IN
AB7
EMMC_CLK
G32
EMMC_CMD
G33
EMMC_RESETN
G31
EMMC_DATA7
D31
EMMC_DATA6
F33
EMMC_DATA5
F32
EMMC_DATA4
E32
EMMC_DATA3
F31
EMMC_DATA2
D33
EMMC_DATA1
D32
EMMC_DATA0
E31
USB2_0_DP0
AN9
USB2_0_DM0
AM9
USB2_0_TXRTUNE
AN8
USB2_1_DP0
H32
USB2_1_DM0
J31
USB2_1_TXRTUNE
H33
USB3_DP0
N31
USB3_DM0
N32
USB3_TXP0
P33
USB3_TXM0
P32
USB3_RXP0
M32
USB3_RXM0
M33
USB3_RESREF0
P31
USB3_DP1
K33
USB3_DM1
K32
USB3_TXP1
L32
USB3_TXM1
L31
USB3_RXP1
K31
USB3_RXM1
J32
USB3_RESREF1
M31
HUB_PORT_OVER0
W28
HUB_VBUS_CTRL0
W29
EB_CS3
H28
EB_CS2
J30
EB_CS1
J28
EB_CS0
J29
EB_WE_N
G30
EB_OE_N
F30
EB_WAIT
H29
EB_BE_N1
G29
EB_BE_N0
G28
CAM_CD1_N
P28
CAM_CD2_N
P27
CAM_CE1_N
U28
CAM_CE2_N
R29
CAM_IREQ_N
V27
CAM_RESET
T28
CAM_INPACK_N
T29
CAM_VCCEN_N
R28
CAM_WAIT_N
U27
CAM_REG_N
N29
EB_ADDR0
K30
EB_ADDR1
E30
EB_ADDR2
M30
EB_ADDR3
N28
EB_ADDR4
M28
EB_ADDR5
M29
EB_ADDR6
L29
EB_ADDR7
K29
EB_ADDR8
K28
EB_ADDR9
L28
EB_ADDR10
D30
EB_ADDR11
F29
EB_ADDR12
C32
EB_ADDR13
C33
EB_ADDR14
C31
EB_ADDR15
B33
EB_DATA0
B32
EB_DATA1
A32
EB_DATA2
B31
EB_DATA3
A31
EB_DATA4
A30
EB_DATA5
B30
EB_DATA6
C30
EB_DATA7
C29
C101
10pF
LOADCAP_ATSC_PCB
C102
10pF
LOADCAP_ATSC_PCB
1
MID_LG1311
2013.04.04
31
M14 Symbol A
PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792 Mhz)
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672 Mhz)
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792 Mhz)
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792 Mhz)
MAIN Clock(24Mhz)
System Configuration
I2C
OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode
Extenal test only
BOOT_MODE0
INSTANT_MODE0
INSTANT boot MODE
"1 : Instant boot
"0 : normal
(internal pull down)
I2C PULL UP
NVRAM
BOOT MODE
"0 : EMMC
"1 : TEST MODE
Write Protection
- Low : Normal Operation
- High : Write Protection
Jtag-0 I/F
System Clock for Analog block(24Mhz)
Extenal test only
PAGE 1
Clock for M14-A0
Jtag-1 I/F
LOCAL DIMMING I2C CONTROL
I2C_1 : AMP
I2C_2 : T-CON,L/DIMING
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB
I2C_5 : NVRAM
I2C_6 : TUNER_MOPLL(T/C,ATV)
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 47LB6500
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