LG 42LY99, Service Manual

Page: 23 / 28

13K
V o l t a g e _ d e t e c t o r
R121-*1
0.1uF C138
47 R186
0.1uF C103
22pF C170
TS_DATA_SYN003:B6;003:C6;003:E3
TP133
GND
TP120
47
R129
100
R197
1.2V
0.1uF C133
0.1uF C115
GIL-G-02P
CON100
READY
1
2
3V3
IRQ2 004:E2
47
AR106
GND
330
R183
I2C_SCL0 001:F9
TS_DATA[3] 003:C5;003:C8;003:E3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
3V3
LDDQM0 002:K4
LDDQS0 002:K4
10K
R154
500-ohm
HH-1M3216-501
L110
V o l t a g e _ d e t e c t o r
0.1uF C156
TP131
0.1uF C178
L102
HH-1M3216-501
TP108
0.01uF
C171
FMILBA
0 0 3 : J 4
L100
HH-1M3216-501
GND
10uF
C167
16V
0.1uF C146
0.1uF C105
100
R196
74LVC14APW
IC102
INVERTER
3
2A
2
1Y
4
2Y
1 1A
6 3Y
5
3A
7
GND
8
4Y
9 4A
10
5Y
11
5A
12
6Y
13
6A
14 VCC
2V5
47 R150
TP146
TP121
1
0
K
R114
0.1uF C119
0.1uF C130
GND
1V2
12K R164
CPU_WAIT 004:F4
47pF C100
10uF
C118
16V
1
2
47
R122
CPU_RST 001:F3
47
AR109
47
R136
3V3
0.1uF C157
0.01uF
C191
0.1uF C144
GND
PIO2B7 004:A8
TP132
12K R121
Cortez_RESET
TP110
47
R137
DTV_AUDIO_MUTE_BUF
FMI_D[0-15]
0.1uF C125
0.1uF C107
FMIGNT 0 0 3 : J 3
I2C_SDA0
004:C5
4.7K R105
GND
READY
R194
I2C_SDA0 001:F9
TP143
L109
FI-C3216-103KJT
OPT R182
TP122
FE_RESET 003:K1
I2C_SDA1
0 0 3 : I 1
L103
HH-1M3216-501
0.1uF C160
10K R175
AR111
47
0.1uF C141
TS_DATA_CLK 003:B7;003:C7;003:E4
LDA[0-12]
002:K2
0.01uF C192
GND
CPU_RST_OUT
001:F3
0.1uF C111
0.1uF C145
DTV_AUDIO_MUTE
0.1uF C186
47 R163
TP142
TP112
32.768KHz
X100
10uF
C166
16V
0.1uF C148 0.1uF C127
TP100
47
R126
2.7K
R143
TS_SEL 003:B4;004:F4
47pF C201
3V3
47 R123
GND
TP148
TS_DATA[4] 003:C5;003:C8;003:E3
27.00000MHz
X101
FMIOE
002:D8;003:J4
0.1uF C179
TP123 10uF
C110
16V
1
2
0.1uF C132
SPDIF_STI_OUT
0.01uF
C172
47
AR101
COMM_UART_RX 0 0 5 : I 5
47
R102
SYS_RST 002:A7
1K R106-*1
V o l t a g e _ d e t e c t o r
3V3
GND
LDBA0 002:K4
LDRAS 002:K4
FMIWE 002:A7
0.1uF C121
0.1uF C123
47
AR104
L104
HH-1M3216-501
TP141
1V2
TS_DATA_VAL 003:B6;003:C6;003:E3
1.2V
4.7K R192
47
R178
TP113
10K
R165
GND
0.1uF C112
OPT R181
0.1uF C147
I2C_SCL1
0 0 3 : I 1
0.01uF
C200
CI_RST 003:E6
TP147
0.1uF C129
LRCLK_DTV
0.1uF C153 0.1uF C120
47 R152
IRQ1 003:F8
TP124
GND
TP101
47 R151
47
AR107
10uF
C168
16V
1.2VA
1V2
0.1uF C173
0.1uF C184
YUV_PIXCLK
0 0 5 : I 4
FMI_A[1-25]
47
R142
GND
1uF
C109
10V
47 R187
TP140
DTV_AUDIO_MUTE 005:D8
2.7K
R149
TP114
0.1uF C174
0.1uF C149
SCLK_DTV
47 R157
0.01uF C176
GND
L108
HH-1M3216-501
OUT_RIGHT
005:H9
10uF
C102
16V
1
2
1.2VA
TP145
1.2VA
0.1uF C128 0.1uF C140
47 AR103
LDWE 002:K4
2K R119-*1
V o l t a g e _ d e t e c t o r
TP125
1.2VA
4.7K
R193
TP102
GND
47
R128
TS_DATA[0] 003:C6;003:C8;003:E3
10K
R167
4.7uF
C198
6.3V
0.1uF C106
2.5V
0.1uF C199
0.01uF
C188
1
0
K
R110
PCMDATA_DTV
TP139
LDD[0-15]
002:K3
GND
ADAC_8V
1V25
3V3
TP115
47
R148
0.1uF C185
I2C_SCL0
004:C5
0.1uF C126
0.1uF C154
TS_DATA[2]
003:C5;003:C8;003:E3
CPU_RST
001:C4
47
R179
TS_DATA[1] 003:C6;003:C8;003:E3
GND
DEBUG_UART_TX 0 0 4 : F 7 ; 0 0 5 : I 5
0.1uF C117
0.1uF C122
47
R139
TP144
3.3V
47
R180
LDCLKE 002:K5
TP126
2.7K
R146
47
AR105
656_D[0-7]
1uF
C104
10V
TP103
LDCLK 002:K5
3.3V
TS_DATA[7] 003:C5;003:C8;003:E3
0.1uF C134
47
R166
0.1uF C152
LDBA1 002:K4
47
R147
0.01uF C190
TP138
0.1uF C158
0.1uF C136
TP116
GND
330K
R155
4.7K R195
47
R140
10K
R168
0
R106
Cortez_RESET
CI_EN
LDCLKN 002:K5
47
AR108
0.1uF C143
0.1uF C150
CVBS
005:D7
1
0
K
R111
GND
120
R124
0.01uF
C175
TP127
TP104
IC101
KIA7029AF
V o l t a g e _ d e t e c t o r
2
G
3
O
1
I
PIO2B6 004:A7
47 R188
0.1uF C163
0.1uF C137
0.1uF C151
LDCAS 002:K4
GND
47
R177
TMUE312GAB
SW100
1 2
4 3
5
DEBUG_UART_RX 0 0 4 : F 6 ; 0 0 5 : I 5
CPU_RST_OUT
001:A5
L106
HH-1M3216-501
TP137
47
R134
DTV_RESET
0.1uF C139
47 R153
0.1uF C131
TP117
2.7K
R145
1uF
C182
10V
GND
2V5
0
R189
0.1uF C159
47
R133
4.7uF
C197
6.3V
0.1uF C180
FMICS1
003:E8
1.2V
AR110 47
0.01uF
C177
TP128
GND
TP105
0.1uF C183
0.1uF C155
0.1uF
16V
C203
10K
R138
FMIREQ 0 0 3 : J 3
47
R131
TS_DATA[5] 003:C5;003:C8;003:E3
GND
0
R119
Cortez_RESET
24LC256-I/SM
IC103
3
A2
2
A1
4
VSS
1 A0
5
SDA
6
SCL
7
WP
8 VCC
0.1uF C135
TP136
0.1uF
C187
1
0
K
R112
0
R170
LDDQM1 002:K4
10pF C169
TP118
FMIBE1 003:K5
0.01uF
C101
TS_DATA[6] 003:C5;003:C8;003:E3
P_3.3V
47
R125
3V3
GND
0.1uF C124
22pF
C195
0.1uF C162
OUT_LEFT
005:H8
L105
HH-1M3216-501
47
R185
LDCS
002:K4
47
AR102
TP129
47
R173
18K
R120
GND
0.1uF C165
TP106
0.1uF C116
330
R184
L101
HH-1M3216-501
FMICS3 002:D8
47
R103
3V3
0.1uF C164
0.1uF C113
LDDQS1 002:K4
TP134
GND
0.01uF
C189
TP119
100pF
50V
C202
10uF
C181
16V
1
2
3V3
COMM_UART_TX 0 0 5 : I 5
47
AR100
0.1uF C114
0.1uF C142
GND
3V3
47 R162
TP130
1
0
K
R113
0.1uF C161
0.1uF C108
TP107
0
R169
GND
10pF
C196
47
R144
TP1147
TP1148
TP1150
TP1493
STI5100GUC
IC100
FMIADDR1
E2
FMIADDR2 E1
FMIADDR3
F3
FMIADDR4
F2
FMIADDR5
F1
FMIADDR6
G3
FMIADDR7
G2
FMIADDR8
G1
FMIADDR9 H3
FMIADDR10
H2
FMIADDR11 H1
FMIADDR12
J 3
FMIADDR13
J 2
FMIADDR14
J 1
FMIADDR15
K3
FMIADDR16
K2
FMIADDR17
K1
FMIADDR18 M3
FMIADDR19
M2
FMIADDR20 M1
FMIADDR21
N3
FMIADDR22
N2
FMIADDR23
N1
FMIADDR24
P3
FMIADDR25
P2
FMIDATA0 T3
FMIDATA1
R3
FMIDATA2 P1
FMIDATA3
U3
FMIDATA4
R2
FMIDATA5
R1
FMIDATA6
V3
FMIDATA7
T2
FMIDATA8
T1
FMIDATA9 W3
FMIDATA10
U2
FMIDATA11
U1
FMIDATA12
V2
FMIDATA13
V1
FMIDATA14
W2
FMIDATA15
W1
LMIADDR0
B17
LMIADDR1 C17
LMIADDR2
A18
LMIADDR3
B18
LMIADDR4
B3
LMIADDR5
A3
LMIADDR6
C4
LMIADDR7
B4
LMIADDR8
A4
LMIADDR9
C5
LMIADDR10 A17
LMIADDR11
B5
LMIADDR12
A5
LMIBA0
B16
LMIBA1
C16
LMIDQM0
B11
LMIDQM1 A11
LMIDQS0
C11
LMIDQS1 B10
NOT_LMICS
A16
NOT_LMIRAS
C15
NOT_LMICAS
B15
LMIRDNOTWR
A15
LMICKEN
C6
LMICLKOUT
B6
NOT_LMICLKOUT A6
LMIVREF
A10
LMIDATA0
B14
LMIDATA1
A14
LMIDATA2
C13
LMIDATA3
B13
LMIDATA4
A13
LMIDATA5
C12
LMIDATA6 B12
LMIDATA7
A12
LMIDATA8
A9
LMIDATA9
B9
LMIDATA10
C9
LMIDATA11
A8
LMIDATA12
B8
LMIDATA13
C8
LMIDATA14
A7
LMIDATA15 B7
PIO0[0]
M19
PIO0[1]
M20
PIO0[2]
N18
PIO0[3]
N19
PIO0[4]
N20
PIO0[5]
P18
PIO0[6]
P19
PIO0[7]
P20
PIO1[0]
V10
PIO1[1]
W10
PIO1[2]
U11
PIO1[3]
Y10
PIO1[4]
Y11
PIO1[5]
W11
PIO1[6]
U12
PIO1[7]
U13
PIO2[0]
R18
PIO2[1]
R19
PIO2[2]
R20
PIO2[3]
T18
PIO2[4]
T19
PIO2[5]
T20
PIO2[6]
U19
PIO2[7]
U20
PIO3[0]
L18
PIO3[1]
L19
PIO3[2]
M18
PIO3[3]
L20
PIO3[4]
C19
PIO3[5]
B20
PIO3[6]
A20
PIO3[7]
C20
PIO4[0]
K4
PIO4[1]
J4
PIO4[2]
H4
PIO4[3]
G4
DAAC1A
V19
DAAC2A
V20
USBDP
J20
USBDM
K20
USBRREF
J19
DONOTCONNECT
F16
NOCONNECT1
E17
NOCONNECT2
F4
NOCONNECT3
H17
NOCONNECT4
K17
NOCONNECT5
L17
NOCONNECT6
M17
NOCONNECT7
U14
NOCONNECT8
U15
NOCONNECT9
U16
GND1
E5
GND2
E6
GND3
E15
GND4
E16
GND5
H8
GND6
H9
GND7
H10
GND8
H11
GND9
H12
GND10
H13
GND11
J8
GND12
J9
GND13
J10
GND14
J11
GND15
J12
GND16
J13
GND17
K8
GND18
K9
GND19
K10
GND20
K11
GND21
K12
GND22
K13
GND23
L8
GND24
L9
GND25
L10
GND26
L11
GND27
L12
GND28
L13
GND29
M8
GND30
M9
GND31
M10
GND32
M11
GND33
M12
GND34
M13
GND35
N8
GND36
N9
GND37
N10
GND38
N11
GND39
N12
GND40
N13
VDDRGB
W15
VDDYCC W14
GNDRGB
V15
GNDYCC
W13
REXTVDACRGB
W16
REXTVDACYCC V13
GNDREXTVDACRGB
V16
GNDREXTVDACYCC
V14
ROUT
Y16
GOUT Y15
BOUT
Y14
YOUT
Y12
COUT
Y13
CVOUT
W12
LRCLK
R17
SCLK U18
PCMCLK
P17
PCMDATA
N17
SPDIF
V18
OUTLEFT Y20
VBGOUT
W20
OUTRIGHT
Y19
CLK27IN
H20
AUXCLKOUT
G20
CLK27OSC
H19
TS0INDATA[7] Y1
TS0INPACKETCLK
Y2
TS0INBITCLKVALID
Y4
TS0INBITCLK
Y5
TS0INERROR
Y3
TS1INDATA[0]
V8
TS1INDATA[1] V7
TS1INDATA[2]
V6
TS1INDATA[3]
W8
TS1INDATA[4]
W7
TS1INDATA[5]
W6
TS1INDATA[6]
Y7
TS1INDATA[7]
Y6
TS1INPACKETCLK V9
TS1INBYTECLKVLD
Y8
TS1INBYTECLK Y9
TS1INERROR
W9
TS2IODATA[0]
T4
TS2IODATA[1]
U4
TS2IODATA[2] U6
TS2IODATA[3]
U7
TS2IODATA[4] U9
TS2IODATA[5]
U5
TS2IODATA[6]
U8
TS2IODATA[7]
U10
TS2IOPACKETCLK
M4
TS2IOBYTECLKVLD
P4
TS2IOBYTECLK
R4
TS2IOERROR N4
NOT_FMIBE0
C2
NOT_FMIBE1
C1
NOT_FMIOE
C3
NOT_FMICSA
A2
NOT_FMICSB
A1
NOT_FMICSC
B2
NOT_FMICSD
B1
FMIRDNOTWR
D3
FMIFLASHCLK
E3
NOT_FMILBA
D2
DCUTRIGOUT
U17
DCUTRIGIN
T17
TMS
V11
TCK
V12
TDI
V17
TDO
W17
NOT_TRST
Y17
NOT_RST
E18
NOT_WDOGRST
H18
IRQ0
V4
IRQ1
W4
DMAREQ0_IRQ2
V5
DMAREQ1_IRQ3
W5
NOT_FMIGRANT
D4
NOT_FMIREQ
E4
FMIWAIT
D1
LPCLKIN
D19
LPCLKOSC
D20
RTCVDD
D18
VDD33_1
F5
VDD33_2
G5
VDD33_3
H5
VDD33_4
H16
VDD33_5
J5
VDD33_6
J16
VDD33_7
K5
VDD33_8
L16
VDD33_9
M5
VDD33_10
M16
VDD33_11
N5
VDD33_12
P5
VDD33_13
P16
VDD33_14
R5
VDD33_15
R16
VDD33_16
T5
VDD33_17
T6
VDD33_18
T7
VDD33_19
T9
VDD33_20
T10
VDD33_21
T11
VDD33_22
T12
VDD33_23
T14
VDD33_24
T15
VDD33_25
T16
VDD25_1
A19
VDD25_2
B19
VDD25_3
C7
VDD25_4
C10
VDD25_5
C14
VDD25_6
C18
VDD25_7
D5
VDD25_8
D6
VDD25_9
D7
VDD25_10
D8
VDD25_11
D9
VDD25_12
D10
VDD25_13
D11
VDD25_14
D12
VDD25_15
D13
VDD25_16
D14
VDD25_17
D15
VDD25_18
D16
VDD25_19
D17
VDD12_1
E8
VDD12_2
E13
VDD12_3
F17
VDD12_4
G16
VDD12_5
G17
VDD12_6
K16
VDD12_7
L1
VDD12_8
L2
VDD12_9
L3
VDD12_10
L4
VDD12_11
L5
VDD12_12
N16
VDD12_13
T8
VDD12_14
T13
VDDDLL
E10
GNDDLL
E11
VDDDE0
E14
VDDDE1
E7
GNDDE0
E12
GNDDE1
E9
VCCAPLL1
F19
VCCAPLL2
F18
GNDAPLL1
E20
GNDAPLL2
E19
VCCAFS
F20
GNDAFS
G18
GNDASFS
G19
USBVDD
K18
USBVSS
K19
USBPLLVDD
J18
USBPLLVSS
J17
VDDADAC
W19
GNDADAC
W18
VPLUSHADAC
Y18
8200pF
C194
8200pF C193
FMI_A[1-25]
FMI_D[0-15]
FMI_A[13]
FMI_A[7]
FMI_A[8]
FMI_A[3]
FMI_A[11]
FMI_A[6]
FMI_A[9]
FMI_A[2]
FMI_A[10]
FMI_A[5]
FMI_A[12]
FMI_A[1]
FMI_A[16]
FMI_A[14]
FMI_A[4]
FMI_D[4]
FMI_D[12]
FMI_D[14]
FMI_D[5]
FMI_D[15]
FMI_D[13]
FMI_D[10]
FMI_D[0]
FMI_D[2]
FMI_D[9]
FMI_D[11]
FMI_D[6]
FMI_D[8]
FMI_D[1]
FMI_D[7]
FMI_D[3]
FMI_A[17]
FMI_A[18]
FMI_A[19]
FMI_A[20]
FMI_A[21]
FMI_A[22]
FMI_A[23]
FMI_A[24]
FMI_A[25]
LDA[0-12]
LDA[12]
LDA[11]
LDA[10]
LDA[9]
LDA[8]
LDA[7]
LDA[6]
LDA[5]
LDA[4]
LDA[3]
LDA[2]
LDA[1]
LDA[0]
LDD[0-15]
LDD[0]
LDD[15]
LDD[1]
LDD[2]
LDD[3]
LDD[4]
LDD[5]
LDD[6]
LDD[7]
LDD[8]
LDD[9]
LDD[10]
LDD[11]
LDD[12]
LDD[13]
LDD[14]
FMI_A[15]
656_D[0]
656_D[1]
656_D[2]
656_D[3]
656_D[4]
656_D[5]
656_D[6]
656_D[7]
S I i 5 1 0 0 D e c o u p l i n g C a p a c i t o r s
For LCD
For PDP
[EEPROM]
EEPROM I2C ADDRESS : Default 0xAA
PULL UP/DOWN
JTAG
O p t i o n f o r r e m o t e c o n t r o l
using Cortez DTV_RESET
1 2 K M u s t b e u s e d i n c a s e o f
R106, R119 --> 0 ohm
L 1 1 0 , L 1 1 1 - - > D e l e t e
1.STi5100
14 STi5100 01
EUROPASS3 2 0 0 7 . 0 8 . 0 3
0.1uF C207 0.1uF C206
0.01uF
C219
0.01uF
C218
0.01uF
C224
0.01uF
C228
0.01uF C230
0.01uF
C204 0.01uF C229
0.01uF
C222
0.01uF
C221
0.01uF
C220
100
R224
100
R214
100
R225
100
R234
100
R241
100
R213
100
R227
100
R202
100
R211
100
R233
100
R218
100
R222
100
R236
100
R221
100
R207
100
R228
100
R203
100
R239
100
R220
100
R204
100
R226
100
R238
100
R231
100
R229
100
R219
100
R235
100
R210
100
R217
100
R201
100
R212
100
R216
100
R209
100
R215
100
R232
100
R208
100
R206
100
R223
100
R237
100
R230
100
R205
4.7K
R200
4.7K
R255
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
MX29LV320CTTC-70G
IC201
ST FLASH
26
CE#
27
GND_1
28 OE#
29 Q0
30
Q8
31
Q1
32
Q9
33
Q2
34
Q10
35
Q3
36 Q11
37 VCC
38
Q4
39
Q12
40
Q5
41
Q13
42
Q6
43
Q14
44 Q7
45 Q15/A-1
46
GND_2
47
BYTE#
48
A16
17
A17
3
A13
6
A10
16
A18
15
RY/BY#
14
WP#/ACC
13 NC
12 RESET#
11
WE#
10
A20
9
A19
8
A8
7
A9
4 A12
5 A11
25
A0
24
A1
23
A2
2
A14
22
A3
21 A4
1
A15
20 A5
19
A6
18
A7
SC2595STR
IC200
3 V_SENSE
2
GND
4
VREF
1 NC
5
VDDQ
6 AVCC
7
PVCC
8 VTT
0.01uF
C231
0.01uF
C233
0.01uF
C232
HYB25D256160CE-5
IC202
26
BA0
27
BA1
28
A10/AP
29
A0
30 A1
31 A2
32 A3
33
VDD_3
34
VSS_1
35 A4
36 A5
37 A6
38
A7
39
A8
40
A9
41
A11
42
NC_5/A12
43 NC_6
44 CKE
45 CK
46
CK
47
UDM
48
VSS_2
49
VREF
50
NC_7
17
NC_2/A13
3
VDDQ_1
6
VSSQ_1
16 LDQS
15 VDDQ_3
14 NC_1
13
DQ7
12
VSSQ_2
11
DQ6
10
DQ5
9
VDDQ_2
8 DQ4
7 DQ3
4
DQ1
5
DQ2
25
NC_4
24 CS0
23 RAS
2
DQ0
22 CAS
21
WE
1
VDD_1
20
LDM
19
NC_3
18
VDD_2
51 UDQS
52 VSSQ_3
53 NC_8
54
DQ8
55
VDDQ_4
56
DQ9
57
DQ10
58
VSSQ_4
59 DQ11
60 DQ12
61
VDDQ_5
62
DQ13
63
DQ14
64
VSSQ_5
65
DQ15
66
VSS_3
100uF
C227
16V
1
2
100uF
C210
16V 1
2
100uF
C226
16V
1
2
10K
R256
GND
TP200
TP201
TP202
TP203
TP204
22
R242
22
R248
22
R243
22
R245
22
R247
22
R244
22
R246
22
AR203
1/16W
22
AR201
1/16W
22
AR205
1/16W
22
AR202
1/16W
22
AR200
1/16W
22
AR204
1/16W
22
AR206
1/16W
22
R251
22 R260
22 R257
22 R259
22 R258
22
R249
22
R250
0 . 1 u F
C234
0 . 1 u F
C241
0 . 1 u F
C235
0 . 1 u F
C242
0 . 1 u F
C236
0 . 1 u F
C243
0 . 1 u F
C237
0 . 1 u F
C238
0 . 1 u F
C239
0 . 1 u F
C240
100
R240
READY
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
10uF
C217
16V
VTT_REPPLE
10uF
C208
16V
VTT_REPPLE
10uF
C213
16V
10uF
C212
16V
10uF
C209
16V
10uF
C216
16V
LD_D[3] 002:C1;002:J2
LD_D[7] 002:G3;002:J3
LD_D[0] 002:C1;002:J2
LD_D[6] 002:G3;002:J3
LD_D[7] 002:C2;002:J3
LD_D[15] 002:H3;002:J3
LD_D[1] 002:G3;002:J2
FMI_D[0-15]
001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004 : I 6 , 0 0 1 : C 5 ; 0 0 3 : G 4 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 3 : G 4 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 3 : G 4 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6 , 0 0 1 : C 5 ; 0 0 4 : I 6
LD_D[1] 002:C1;002:J2
LD_D[11] 002:C2;002:J3
LD_D[9] 002:H3;002:J3
LD_D[2] 002:G3;002:J2
LD_D[9] 002:C2;002:J3
LD_D[13]
002:H3;002:J3
LD_D[4] 002:G3;002:J2
LD_D[10] 002:C2;002:J3
LDD[0-15]
001:D7
LD_D[12] 002:C2;002:J3
LD_D[8] 002:H3;002:J3
LD_D[3] 002:G3;002:J2
LD_D[15] 002:C2;002:J3
LD_D[11] 002:H3;002:J3
LD_DQS1 002:C4;002:J4
LD_D[14] 002:C2;002:J3
LD_D[8] 002:C2;002:J3
LD_D[0] 002:G3;002:J2
LD_D[12] 002:H3;002:J3
LD_D[13] 002:C2;002:J3
LD_D[4] 002:C1;002:J2
LD_D[5] 002:G3;002:J3
LD_D[2] 002:C1;002:J2
LD_D[14] 002:H3;002:J3
LD_D[5] 002:C1;002:J3
LD_D[10] 002:H3;002:J3
LD_D[6] 002:C2;002:J3
LD_A[1] 002:G4;002:J1
LD_A[4]
002:H5;002:J2
LD_A[1] 002:C2;002:J1
LD_A[7] 002:H4;002:J1
LD_CS 002:G4;002:J4
LD_A[0] 002:C2;002:J1
LD_A[8] 002:H4;002:J2
LD_BA0 002:G4;002:J4
LD_A[10] 002:C3;002:J1
LD_A[12] 002:H4;002:J2
LD_A[0] 002:G4;002:J1
LD_BA1 002:C3;002:J4
FMI_A[1-25]
001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,0 01:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4 ;003:K5,001:C4;003:K5,001:C4;004:J4,001:C4;004:J4,001:C4;004:J4,001:C4;004:G2,001:C4;004:G2,001:C4,00 1:C4,001:C4,001:C4
SYS_RST 001:B6
FMIWE 001:D3
LD_BA0 002:C3;002:J4
LDCLKN
001:D7
FMIOE 001:D3;003:J4
FMICS3 001:D3
LDA[0-12]
001:C6
LD_CS 002:C4;002:J4
LDCLK 001:D7
LDBA0 001:D6
LD_A[4]
002:C3;002:J2
LD_RAS 002:C4;002:J4
LD_A[5]
002:C3;002:J1
LD_CAS 002:C4;002:J4
LD_WE 002:G4;002:J4
LD_A[6] 002:C3;002:J1
LD_WE 002:C4;002:J4
LD_A[11] 002:H4;002:J2
LDRAS 001:D6
LD_A[7] 002:C3;002:J1
LD_DQM0 002:C4;002:J4 LDCS 001:D6
LDWE 001:D7
LD_A[8] 002:C3;002:J2
LD_DQM0 002:G4;002:J4
LD_A[3] 002:G5;002:J1
LD_DQS0 002:C4;002:J4
LDDQS1 001:D6
LDCAS 001:D7
LD_A[9] 002:C3;002:J2
LD_BA1 002:G4;002:J4
LD_CLK 002:H4;002:J5
LDDQM1 001:D6
LD_A[11] 002:C3;002:J2
LD_A[2] 002:G4;002:J1
LD_A[5] 002:H4;002:J1
LDDQM0 001:D6
LD_DQS1 002:H4;002:J4
LD_A[12] 002:C3;002:J2
LD_DQM1 002:H4;002:J4
LDDQS0 001:D6
LD_CLKE
002:D5;002:J5
LD_RAS
002:G4;002:J4
LD_A[2] 002:C3;002:J1
LDBA1 001:D6
LD_CLK 002:C4;002:J5
LD_A[10] 002:G4;002:J1
LD_CLKN 002:H4;002:J5
LD_CLKN 002:D5;002:J5
LD_A[6] 002:H4;002:J1
LDCLKE 001:D7
LD_DQM1 002:C4;002:J4
LD_A[9] 002:H4;002:J2
LD_CAS 002:G4;002:J4
LD_A[3] 002:C3;002:J1
LD_CLKE 002:H4;002:J5
LD_DQS0 002:G4;002:J4
LD_D[11] 002:C2;002:H3
LD_D[8] 002:C2;002:H3
LD_A[8] 002:C3;002:H4
LD_A[2] 002:C3;002:G4
LD_D[5] 002:C1;002:G3
LD_DQS0 002:C4;002:G4
LD_DQM1 002:C4;002:H4
LD_DQM0 002:C4;002:G4
LD_D[2] 002:C1;002:G3
LD_WE 002:C4;002:G4
LD_A[10] 002:C3;002:G4
LD_A[0] 002:C2;002:G4
LD_D[1] 002:C1;002:G3
LD_DQS1 002:C4;002:H4
LD_CS 002:C4;002:G4
LD_D[3] 002:C1;002:G3
LD_BA0 002:C3;002:G4
LD_A[9] 002:C3;002:H4
LD_CAS 002:C4;002:G4
LD_D[15] 002:C2;002:H3
LD_A[12] 002:C3;002:H4
LD_CLKE 002:D5;002:H4
LD_D[14] 002:C2;002:H3
LD_A[6] 002:C3;002:H4
LD_D[13] 002:C2;002:H3
LD_CLKN
002:D5;002:H4
LD_D[12] 002:C2;002:H3
LD_CLK 002:C4;002:H4
LD_A[4] 002:C3;002:H5
LD_D[10] 002:C2;002:H3
LD_A[7] 002:C3;002:H4
LD_D[9] 002:C2;002:H3
LD_RAS 002:C4;002:G4
LD_D[4] 002:C1;002:G3
LD_D[6] 002:C2;002:G3
LD_BA1 002:C3;002:G4
LD_A[11] 002:C3;002:H4
LD_D[7] 002:C2;002:G3
LD_A[1] 002:C2;002:G4
LD_A[5] 002:C3;002:H4
LD_A[3] 002:C3;002:G5
LD_D[0] 002:C1;002:G3
2V5 VTT
1V25
3V3
3V3
2V5 2V5
2V5
VTT
1V25
FMI_A[16]
FMI_A[15]
FMI_A[14]
FMI_A[13]
FMI_A[12]
FMI_A[11]
FMI_A[10]
FMI_A[9]
FMI_A[20]
FMI_A[21]
FMI_A[22]
FMI_A[19]
FMI_A[18]
FMI_A[8]
FMI_A[7]
FMI_A[6]
FMI_A[5]
FMI_A[4]
FMI_A[3]
FMI_A[2]
FMI_A[17]
FMI_D[0-15]
FMI_D[0]
FMI_D[8]
FMI_D[1]
FMI_D[9]
FMI_D[2]
FMI_D[10]
FMI_D[3]
FMI_D[11]
FMI_D[4]
FMI_D[12]
FMI_D[5]
FMI_D[13]
FMI_D[6]
FMI_D[14]
FMI_D[7]
FMI_D[15]
FMI_A[1]
LDA[0-12]
LDA[10]
LDA[3]
LDA[2]
LDA[1]
LDA[0]
LDA[7]
LDA[6]
LDA[5]
LDA[4]
LDA[12]
LDA[11]
LDA[9]
LDA[8]
LDD[0]
LDD[1]
LDD[2]
LDD[3]
LDD[7]
LDD[6]
LDD[5]
LDD[4]
LDD[11]
LDD[10]
LDD[8]
LDD[12]
LDD[13]
LDD[14]
LDD[15]
LDD[9]
DDR Termination Power
DDR Termination Resistors
DDR SDRAM 16MB/32MB/64MB
BOOT FLASH 4MB/8MB
V T T D e c o u p l i n g C a p a c i t o r s
DDR TERMINATION OPTIONs
PDP 12.07
D D R S e r i e s R e s i s t o r s
2.ST DDR
14 ST DDR 02
EUROPASS3 2 0 0 7 . 0 6 . 0 7
R412
47
47
R413
0.1uF
C405
READY
0.1uF
C407
READY
C409
0.1uF
16V
C411
0.1uF
16V
0.1uF
C404
READY
0.1uF
C406 READY
C410
0.1uF
16V
0.1uF
C403
16V
READY
C408
0.1uF
READY
IC404
74LVC14APW
INVERTER
3
2A
2 1Y
4
2Y
1
1A
6
3Y
5 3A
7 GND 8 4Y
9
4A
10 5Y
11
5A
12
6Y
13 6A
14
VCC
0
R416
0
R417
1K
R415
1K
R414
47
R421
Q401
2SC3875S
1
E
2
B
3 C
2SC3875S
Q402
1 E
2
B
3
C
Q400
2SC3875S
1
E
2B
3 C
R419 READY
R420
READY
10K
R403
12K
R407
IC401
ICL3232CBNZ
READY
3 C1-
2
V+
4
C2+
1
C1+
6 V-
5
C2-
7
T2OUT
8 R2IN 9 R2OUT
10
T2IN
11 T1IN
12
R1OUT
13
R1IN
14 T1OUT
15
GND
16
VCC
IC403
74LVC32AD
OR gate
3
1Y
2 1B
4
2A
1
1A
6
2Y
5
2B
7 GND 8 3Y
9
3A
10
3B
11
4Y
12
4B
13 4A
14
VCC
0.1uF
16V
C415
10uF
16V
C414 1
2
HH-1M3216-501
L400
1/10W
4.7K
5%
R422
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
R438
TC74LCX157FT
IC410
3
2
4
1
6
5
7
8 9
10
11
12
13
14
15
16
0.1uF C430
LRCLK_DTV
HDMI_LRCK
LRCLK_MUX
PCMDATA_DTV
HDMI_LRCH
PCMDATA_MUX
SCLK_DTV
HDMI_SCK
SCLK_MUX
3_STATE_BUFFER
SPDIF_OUT
SPDIF_OUT
IC402
TC74LCX08FT
AND GATE
3
1Y
2 1B
4
2A
1
1A
6
2Y
5 2B
7 GND 8 3Y
9
3A
10 3B
11
4Y
12
4A
13 4B
14
VCC
JP400
22
R437
0.1uF C429
JP401
R455 READY
R456 READY
C432
READY
C433
READY
C434
READY
C435
READY
100 R448
100 R439
100 R441
100 R446
P_3.3V
GND
0.1uF
16V
C413
10uF
16V
C4121
2
35337-0320
CON400
READY
1
2
3
GND
TP400
TP401
TP402
TP403
TP404
TP405
TP406
TP407
TP408
TP409
TP410
TP411
TP412
TP413
TP414
TP415 TP416
TP417
TP430
TP431
TP432
TP433
TP434
TP435
TP449
TP444
TP447
TP446
TP445
TP442
TP443
TP439
TP436
TP440
TP441
TP453
TP456
TP455
TP454
TP452
TP451
TP450
TP458
TP457
TP459
TP460
TUNER_ERROR
TP461
SPDIF
J400
o p t i c j a c k
4
INPUT
3
GND
2
GND
6 5V
1
GND
5 GND
TP469
TP468
TP467
TP466 TP465
TP464
TP463
TP462
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPDIF_MSP_OUT
SPDIF_STI_OUT
CI_CS
003:F8;003:H6;003:I4;003:K3;003:K6
TS_SEL
001:F8;003:B4
CI_CD2 003:E7
CI_OE 003:H6;003:L3
CI_WAIT
003:E6
FE_TS_DATA_VAL
003:H6;003:L3
CI_IORD 003:E6;003:L4
PIO2B7
001:F8
CI_CD1 003:E5
DEBUG_UART_TX
PIO2B6
001:F8
D_T/R 003:G3
REC_8
013:C8
IRQ2 001:E2
CPU_WAIT
001:F2
FE_TS_DATA_VAL_AND_ERR
003:G3
DEBUG_UART_RX
TS_SEL_CI
003:B7
CI_LATCH 003:K6
3V3_CI
3V3_CI
3V3_CI
3V3_CI 3.3V
5.0V
P_12V
3V3_CI
JP1148
JP1149
TP1151
TP1363
OPTION
P I 4 [ 0 ]
P I 4 [ 1 ]
STi5100
[SCART PIN8]
5.19V / 10.91V_1Kohm(LOAD)
4.89V / 9.09V_120ohm(LOAD)
CI OPTIONs(UK)
IF YOU WANT TO USE CN401, R449,R450 -> 0 Ohm ADD
R 5 4 3 , R 5 4 4 - > D E L E T E
TO MSP
SPDIF OPTIC JACK
OPTION
LOW
3Y
1A
GND
2A
HIGH
3B 2Y
1Y
VCC
3A
ST
SEL
1B
2B
4A
4B
4Y
ST UART FOR DEBUG I2S SWITCHING (DTV&HDMI)
O p t i o n f o r r e m o t e c o n t r o l
4.ATAPI/UART/FAN
14 04
EUROPASS3
ATAPI/UART
2 0 0 7 . 0 6 . 0 7
74LVC541A(PW)
BUFFER
IC300
3
A1
2
A0
4
A2
1
OE1
6
A4
5 A3
7
A5
8
A6
9
A7
10 GND 11 Y7
12
Y6
13
Y5
14
Y4
15
Y3
16 Y2
17
Y1
18
Y0
19
OE2
20
VCC
74LVC541A(PW)
BUFFER
IC302
3 A1
2
A0
4
A2
1
OE1
6
A4
5
A3
7
A5
8 A6
9
A7
10
GND
11
Y7
12
Y6
13 Y5
14
Y4
15
Y3
16
Y2
17
Y1
18 Y0
19
OE2
20
VCC
74LVC245A
IC304
Bidirec(High:A->B)
3
A1
2 A0
4 A2
1
DIR
6
A4
5
A3
7 A5
8
A6
9 A7
10
GND
11
B7
12 B6
13
B5
14 B4
15
B3
16
B2
17 B1
18
B0
19 OE
20
VCC
R327 33
0.1uF C303
0.1uF
C314
0.1uF C307
0.1uF
C313
0.1uF
C309
0.1uF C310
0.1uF
C302
0.1uF
C308 0.1uF
C306
0.1uF
C312
0.1uF C311
0.1uF C301
74LCX244MTC
IC301
B u f f e r
3
O4
2 I 0
4
I 1
1
OE1
6
I 2
5
O5
7 O6
8
I 3
9
O7
10
GND
11
I 7
12
O3
13
I 6
14 O2
15
I 5
16
O1
17
I 4
18
O0
19 OE2
20
VCC
74LCX244MTC
IC303
B u f f e r
3
O4
2
I 0
4
I 1
1 OE1
6 I 2
5
O5
7
O6
8
I 3
9 O7
10
GND
11
I 7
12 O3
13
I 6
14
O2
15 I 5
16
O1
17
I 4
18
O0
19
OE2
20 VCC
R314
0
100 R325
100
R324
100 R326
R304
10K
R320
10K
10K R319
10K R303
10K R305
10K
R329
10K
R302
R306 10K
R301 47
47 R310
47 R313
47 R312
47
R321
47 R311
47 R323
47 R315
47 R309
47 R322
R31647
OPT
R307
OPT R308 OPT R318
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FE_TS_DATA[0-7],FE_TS_DATA_CLK,FE_TS_DATA_VAL,FE_TS_DATA_SYN
74LCX373MTCX_NL
IC306
3
D0
2
O0
4
D1
1
OE
6
O2
5 O1
7
D2
8
D3
9
O3
10 GND 11 LE
12
O4
13
D4
14
D5
15
O5
16 O6
17
D6
18
D7
19
O7
20
VCC
74LCX373MTCX_NL
IC305
3
D0
2
O0
4
D1
1
OE
6
O2
5 O1
7
D2
8
D3
9
O3
10 GND 11 LE
12
O4
13
D4
14
D5
15
O5
16 O6
17
D6
18
D7
19
O7
20
VCC
91932-31169LF
CN300
57
21
52
16
10
47
41
5
36
59
23
45
54
18
49
43
13
7
38
2
25
56
20
51
15
9
46
40
4
35
58
22
53
17
11
48
42
12
6
37
1
24
55
19
50
44
14
8
39
3
26
60
27
61
28
62
29
63
30
64
31
32
33
34
65
66
67
68
69
70
5.0V_CI
33
AR303
1
2
3
4 5
6
7
8
33AR305
1
2
3
4 5
6
7
8
33
AR306
1
2
3
4 5
6
7
8
33
AR304
1
2
3
4
5
6
7
8
33
AR307
1
2
3
4 5
6
7
8
AR313 33
1/16W
33
AR311
1/16W
33 AR309
1/16W
33
AR312
1/16W
AR314
33
1/16W
33
AR310
1/16W
33
AR308
1/16W
TP371
TP372
TP373
TP374
TP375
TP376
TP377
TP378
TP300
TP301
TP302
TP303
TP304
TP305
TP306
TP307
TP308
TP309
TP310
TP311
TP312
TP313
TP314
TP315
TP316
TP317
TP318
TP319
TP320
TP321
TP322
TP323
TP324
TP325
TP326
TP327
TP328
TP329
TP330
TP331
TP332
TP333
TP334
TP335
TP336
TP337
TP338
TP339
TP340
TP341
TP342
TP343
TP344
TP345
TP346
TP347
TP348
TP349
TP350
TP351
TP352
TP353
TP354
TP355
TP356
TP357
TP358
TP359 TP360
TP361 TP362
TP363
TP364
TP365
TP366
TP367
TP368
TP369
TP370
TP387
TP386
TP385
TP384
TP383
TP382
TP381
TP379
TP380
GND1
1 35
GND3 36
D3
2
CD1
37 D4 3 D11/MDO3
38
D5
4
D12/MDO4
39 D6 5 D13/MDO5
40
D7
6
D14/MDO6
41 CE1 7 D15/MDO7
42
A10
8
CE2/EXT_CH
43 OE 9 VS1
44
A11
10
IORD/RFU 45
A9/DRX
11
IOWR/RFU
46 A8/CRX 12 A17/MISTRT
47
A13
13
A18/MDI0
48 A14 14 A19/MDI1
49
WE
15
A20/MDI2
50 IREQ/READY 16 A21/MDI3
51
VCC3.3V1
17
VCC3.3V2 52
VPP1/SW5V1
18
VPP/SW5V2
53
A16/MIVAL
19
A22/MDI4 54
A15/MCLKI
20
A23/MDI5
55 A12 21 A24/MDI6
56
A7/QTX
22
A25/MDI7
57 A6/ETX 23 VS2/MCLKO
58
A5/ITX
24
RESET
59 A4/CTX 25 WAIT
60
A3
26
INPACK 61
A2
27
REG
62
A1
28
MOVAL/BVD2 63
A0
29
MOSTRT/BVD1
64 D0 30 D8/MDO0
65
D1
31
D9/MDO1
66 D2 32 D10/MDO2
67
IOIS16/WP
33
CD2
68 GND2 34 GND4
74031-118CALF
P300
CI_SLOT
G1 G2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
FMI_D[0-7]
001:C5;002:D6;004:I6
CI_WE 003:L3
CI_IORD
003:L4;004:E3
FE_TS_DATA_VAL_AND_ERR
CI_IOWR 003:L4
FE_TS_DATA_CLK_BUF
CI_TS_DATA[3] 003:E7
CI_TS_DATA[1] 003:E7
CI_TS_DATA[7] 003:E6
CI_TS_DATA[0] 003:E7
CI_TS_DATA[4] 003:E6
CI_TS_DATA[2] 003:E7
CI_TS_DATA[6] 003:E6
REG 0 0 3 : I 8
CI_RST 001:H8
CI_CS
003:F8;003:I4;003:K3;003:K6;004:G4
FMIBE1,FMI_A[1-16]
CI_CS
003:F8;003:H6;003:I4;003:K6;004:G4
FMIGNT
D_T/R
004:E3
CI_CS
CI_LATCH
CI_CS
CI_OE
003:L3;004:E3
CI_IRQ
FMIREQ
FMILBA
001:D3
CI_TS_DATA_CLK
CI_TS_DATA_VAL
FMIOE
CI_TS_DATA_SYN
TS_SEL_CI 004:F4
TS_SEL
001:F8;004:F4
FMICS1
CI_TS_DATA[5] 003:E6
CI_WE
CI_IOWR
CI_OE
CI_IORD
FE_TS_DATA_CLK_BUF
CI_CS
REG 003:E7
TS_DATA[1] 001:K6;003:C5;003:E3
TS_DATA[4] 001:K7;003:C5;003:E3
TS_DATA[0] 001:K6;003:C5;003:E3
TS_DATA[6] 001:K7;003:C6;003:E3
TS_DATA[2] 001:K6;003:C5;003:E3
TS_DATA[3] 001:K6;003:C5;003:E3
TS_DATA[7] 001:K7;003:C6;003:E3
TS_DATA[5] 001:K7;003:C5;003:E3
CI_IRQ 003:F8
CI_TS_DATA[4]
003:B8
CI_TS_DATA[1]
003:B8
CI_TS_DATA_CLK
003:C7
CI_TS_DATA_SYN
003:C6
CI_TS_DATA[3]
003:B8
CI_TS_DATA[0]
003:B8
CI_CD2
004:E2
CI_TS_DATA[5]
003:B8
CI_TS_DATA_VAL 003:C7
CI_TS_DATA[2]
003:B8
CI_WAIT
004:F3
CI_CD1
004:E2
CI_TS_DATA[7]
003:B8 CI_TS_DATA[6]
003:B8
TS_DATA_VAL
TS_DATA_CLK
TS_DATA_SYN TS_DATA_SYN
TS_DATA_VAL
TS_DATA_CLK
TS_DATA[6] 001:K6;003:C8;003:E3
TS_DATA[1] 001:K7;003:C8;003:E3
TS_DATA[7] 001:K6;003:C8;003:E3
TS_DATA[4] 001:K6;003:C8;003:E3
TS_DATA[5] 001:K6;003:C8;003:E3
TS_DATA[0] 001:K7;003:C8;003:E3
TS_DATA[2] 001:K7;003:C8;003:E3
TS_DATA[3] 001:K7;003:C8;003:E3
IRQ1
5.0V
5.0V
5.0V
3V3_CI
3V3_CI
3V3_CI
3V3_CI
3V3_CI
TP1142
TP1143
TP1144
TP1145
TP1146
TP1149
TP1156
TP1157
TP1492
TP1494
TP1495
TP1496
TP1497
TP1498
TP1499
TP1500
TP1515
TP1568
TP1569
TP1570
TP1571
TP1572
TP1573
TP1574
TP1575
TP1576
TP1577
TP1578
TP1579
TP1580
TP1581
TP1582
TP1583
TP1584
TP1585
TP1586
TP1587
TP1588
TP1589
CI_DATA[5]
CI_DATA[2]
CI_DATA[4]
CI_DATA[3]
CI_ADDR[0]
CI_DATA[0]
CI_ADDR[0-14]
CI_ADDR[2]
CI_DATA[7]
T_ADDR[0-16]
CI_DATA[1]
CI_DATA[6]
CI_ADDR[1]
T_ADDR[12]
FMI_A[12]
FMI_A[13]
T_ADDR[13]
T_ADDR[14]
FMI_A[14]
T_ADDR[4]
FMI_A[4]
FMI_A[5]
T_ADDR[5]
T_ADDR[6]
FMI_A[6]
FMI_A[7]
T_ADDR[7]
CI_DATA[1]
CI_DATA[0]
CI_DATA[4]
CI_DATA[3]
FMIBE1,FMI_A[1-16]
FMIBE1,FMI_A[1-16]
FMI_A[8]
FMI_A[9]
FMI_A[10]
FMI_A[11]
FMI_A[2]
FMIBE1
FMI_A[1]
T_ADDR[0]
T_ADDR[1]
T_ADDR[2]
T_ADDR[3]
T_ADDR[8]
T_ADDR[9]
T_ADDR[11]
CI_ADDR[0]
CI_ADDR[1]
CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]
CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[14]
CI_ADDR[13]
FMI_A[3]
CI_DATA[0-7]
FMI_A[16]
T_ADDR[16]
CI_ADDR[0-14]
FMI_D[0]
FMI_D[2]
FMI_D[7]
FMI_D[5]
FMI_D[1]
FMI_D[3]
FMI_D[6]
FMI_D[4]
FMI_D[0-7]
T_ADDR[16]
CI_DATA[5]
CI_DATA[6]
CI_DATA[7]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[9]
CI_ADDR[8]
CI_ADDR[13]
CI_ADDR[14]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[12]
CI_DATA[2]
T_ADDR[10]
FE_TS_DATA[7]
FE_TS_DATA[6]
FE_TS_DATA[5]
FE_TS_DATA[4]
FE_TS_DATA[3]
FE_TS_DATA[2]
FE_TS_DATA[1]
FE_TS_DATA[0]
FE_TS_DATA_CLK
FE_TS_DATA_SYN
FE_TS_DATA_VAL
FE_TS_DATA[0-7],FE_TS_DATA_CLK,FE_TS_DATA_VAL,FE_TS_DATA_SYN
FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
FE_TS_DATA[4]
FE_TS_DATA[5]
FE_TS_DATA[6]
FE_TS_DATA[7]
FE_TS_DATA_SYN
T_ADDR[0]
T_ADDR[1]
T_ADDR[2]
T_ADDR[3]
T_ADDR[4]
T_ADDR[5]
T_ADDR[6]
T_ADDR[7]
T_ADDR[8]
T_ADDR[9]
T_ADDR[10]
T_ADDR[11]
T_ADDR[12]
T_ADDR[13]
T_ADDR[14]
FE_TS_DATA_CLK
FE_TS_DATA_CLK_BUF
FE_TS_DATA[0-7],FE_TS_DATA_CLK,FE_TS_DATA_VAL,FE_TS_DATA_SYN
CI OPTIONs(UK)
3 . C I
03
EUROPASS3
CI 14
2 0 0 7 . 0 6 . 0 7