THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
RXD3-
RXA4+
C-MODT
RXB4+
C-TMA12
C-TMBA2
RXC4+
C-TMODT
C-TMDQU7
C319
0.1uF
C-MA6
C-MDQU5
C-TMCK
C-MA9
C-MA3
C-MDQSU
R317
820
C322
0.1uF
C313
0.1uF
C-MDQU1
C-TMA4
C-MA12
C-TMA3
C-MDQSUB
C-TMA6
FRC_CONF1
C324
10uF
10V
C-TMDQU4
C-TMA1
VCC1.5V_U3_DDR
RXA0-
TP301
C323
0.1uF
C-TMDQL4
RXACK+
C-MA1
C-MA12
RXA0+
C-MCK
UART_FRC_RX
C-TMBA2
RXCCK-
R323 1K
C310
0.1uF
C-MDQL1
UART_FRC_TX
C306
0.1uF
C-TMDQL7
C317
0.1uF
C-MDQU4
C-TMCKB
C-MDMU
C-MCKE
C320
0.1uF
RXB0+
C-MA8
C-TMA6
RXB1+
R306
150
OPT
C-TMA4
C302
0.1uF
C-MDQL1
C-TMCKE
C-MDQSL
C-MA10
RXC3+
FRC_PWM0
C-TMODT
C-TMDML
C-MDQSLB
C-TMDQSLB
C-MA11
C-TMDMU
R303
240
1%
C-TMCASB
FRC_CONF0
RXD2-
C-TMA12
C-TMA7
C-TMCKB
C-MA6
VCC1.5V_U3_DDR
C-TMDQSLB
C-TMA1
C318
0.1uF
RXD1+
RXBCK-
GVDD_EVEN
R300
0
OPT
C-TMBA1
FRC_PWM1
C-TMDQU3
C-TMDQL4
RXCCK+
TP302
C316
0.1uF
RXC1-
C-TMA0
C-MDQL7
RXB2-
C-TMDQU3
C-MRASB
+3.3V_Normal
C-MDMU
C-MBA0
C-MDQU7
C-TMWEB
C-MDQU2
GCLK2
C-MCKB
C-TMA11
R305
1K
1%
R301
1K
1%
C-TMA2
C-TMDQU7
C-TMDQL2
GCLK4
I2C_SDA
C-MDQU2
RXA3-
C-TMDQU6
C-TMA5
C-MA10
C325
0.1uF
16V
RXC3-
RXA1+
RXB1-
C-TMCKE
C-MDQSU
C-MA7
C-TMRESETB
C-MBA0
C-MVREFDQ
C-MCKB
RXB4-
C-MDQL0
C-TMDQU2
C-TMDQL3
R322 1K
OPT
C-TMBA1
C-TMDQSUB
R318
1K
C-MDQU3
C-MA3
C-MA0
C-TMDQSU
C-TMDQSU
C-TMA0
C-MRESETB
C-MDQU4
C-MDQL5
C314
1000pF
C-TMDML
RXC2+
RXC1+
C-TMDQL1
C-MRASB
C-TMDQL7
RXD3+
RXD4+
C-TMA2
R302
1K
1%
C-TMRASB
C-MDQL3
C305
0.1uF
C-TMCASB
C-MDQU6
C-MDQSUB
C-TMDQU5
C-MCASB
C-MDQU1
C-MA5
RXB3+
RXDCK-
RXD0+
C-TMA7
RXC4-
C-TMDQL1
C-MVREFCA
R319
1K
OPT
RXC2-
C-MDQSL
C-TMCK
C-MDQL6
C-TMDQL6
RXBCK+
RXB2+
C-MDQL4
C-MDQL4
C-TMDQL0
C-MDQU6
C-TMRASB
C-MA0
VCC1.5V_U3_DDR
C-TMA9
C-MA2
C-MVREFCA
C-TMDQU5
C-MA11
C-TMDQU4
C-TMRESETB
RXD0-
VCC1.5V_U3_DDR
C311
0.1uF
C-MODT
C-MDQU5
C315
0.1uF
C-MA4
C-MDQL5
C-TMDQL2
RXA2-
C-TMDQL5
C-MBA1
C-TMDQU0
C-TMA9
R304
1K
1%
C-TMDQU2
C-MDQU0
RXDCK+
C-MDQU3
DPM_A
C-MDQSLB
C-TMA10
C-MA1
C-MBA2
C-MDQL2
C-MDQL6
C309
0.1uF
RXB0-
RXA4-
C-MA4
C-TMDQL3
C-MA2
C321
0.1uF
C-MBA2
C-TMBA0
RXA2+
C-TMA11
C-TMA8
+1.5V_FRC_DDR
RXD2+
RXD4-
C-MA7
C303
0.1uF
C-MA8
FRC_CONF0
C-MDQL3
C-MWEB
RXC0+
C-TMWEB
C312
0.1uF
RXA1-
RXC0-
C-MCASB
C-MDQU7
FRC_CONF1
C-TMA8
C301
10uF
C304
1000pF
C-MDQL0
C-TMA10
C-MVREFDQ
RXA3+
C-MDQL2
L301
C-MA5
C-TMDQU0
C-MCK
C-MDQU0
C-TMDQL0
R320 1K
C-MA9
RXD1-
RXB3-
C-MCKE
C-TMDQU1
R321 1K
OPT
C-TMDQL6
FRC_PWM1
C-TMBA0
RXACK-
C-MDML
GVDD_ODD
I2C_SCL
C-TMA3
C-MRESETB
C307
0.1uF
C-TMDQSL
C-TMDQU1
C-TMDQL5
C-TMA5
C-TMDQU6
C-TMDMU
R324
1K
OPT
R325
1K
C-TMDQSL
C-MBA1
C-TMDQSUB
VCC1.5V_U3_DDR
FRC_PWM0
C-MWEB
C-MDML
C-MDQL7
C308
0.1uF
V_SYNC
R332
0
VCC1.5V_U3_DDR
R333
10K
R314
10
R313
10
R310
10
R308
10
R315
10
R311
10
R316
10
R307
10
R312
10
R309
10
AR302
10
AR309
10
AR303
10
AR306
10
AR305
10
AR301
10
AR307
10
AR308
10
AR304
10
FRC_SDA
R335
22
OPT
R334
22
OPT
FRC_SCL
R336
0
MINI_LVDS
R326
22
FRC
R331
22
FRC
H5TQ1G63BFR-12C
IC301
FRC_DDR_1600
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
R327
0
R328
0
H5TQ1G63BFR-H9C
IC301-*1
FRC_DDR_1333
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
LGE107D (S7M Divx_Non RM)
IC101
S7M_DIVX & MS10
FRC_DDR3_A0/DDR2_NC
AE1
FRC_DDR3_A1/DDR2_A6
AF16
FRC_DDR3_A2/DDR2_A7
AF1
FRC_DDR3_A3/DDR2_A1
AE3
FRC_DDR3_A4/DDR2_CASZ
AD14
FRC_DDR3_A5/DDR2_A10
AD3
FRC_DDR3_A6/DDR2_A0
AF15
FRC_DDR3_A7/DDR2_A5
AF2
FRC_DDR3_A8/DDR2_A2
AE15
FRC_DDR3_A9/DDR2_A9
AD2
FRC_DDR3_A10/DDR2_A11
AD16
FRC_DDR3_A11/DDR2_A4
AD15
FRC_DDR3_A12/DDR2_A8
AE16
FRC_DDR3_BA0/DDR2_BA2
AF3
FRC_DDR3_BA1/DDR2_ODT
AF14
FRC_DDR3_BA2/DDR2_A12
AD1
FRC_DDR3_MCLK/DDR2_MCLK
AD13
FRC_DDR3_CKE/DDR2_RASZ
AE14
FRC_DDR3_MCLKZ/DDR2_MCLKZ
AE13
FRC_DDR3_ODT/DDR2_BA1
AE4
FRC_DDR3_RASZ/DDR2_WEZ
AD5
FRC_DDR3_CASZ/DDR2_CKE
AF4
FRC_DDR3_WEZ/DDR2_BA0
AD4
FRC_DDR3_RESETB/DDR2_A3
AE2
FRC_DDR3_DQSL/DDR2_DQS0
AF8
FRC_DDR3_DQSLB/DDR2_DQSB0
AD9
FRC_DDR3_DQSU/DDR2_DQS1
AE9
FRC_DDR3_DQSUB/DDR2_DQSB1
AF9
FRC_DDR3_DML/DDR2_DQ7
AE11
FRC_DDR3_DMU/DDR2_DQ11
AF6
FRC_DDR3_DQL0/DDR2_DQ6
AE6
FRC_DDR3_DQL1/DDR2_DQ0
AF11
FRC_DDR3_DQL2/DDR2_DQ1
AD6
FRC_DDR3_DQL3/DDR2_DQ2
AD12
FRC_DDR3_DQL4/DDR2_DQ4
AE5
FRC_DDR3_DQL5/DDR2_NC
AF12
FRC_DDR3_DQL6/DDR2_DQ3
AF5
FRC_DDR3_DQL7/DDR2_DQ5
AE12
FRC_DDR3_DQU0/DDR2_DQ8
AE10
FRC_DDR3_DQU1/DDR2_DQ14
AF7
FRC_DDR3_DQU2/DDR2_DQ13
AD11
FRC_DDR3_DQU3/DDR2_DQ12
AD7
FRC_DDR3_DQU4/DDR2_DQ15
AD10
FRC_DDR3_DQU5/DDR2_DQ9
AE7
FRC_DDR3_DQU6/DDR2_DQ10
AF10
FRC_DDR3_DQU7/DDR2_DQM1
AD8
FRC_DDR3_NC/DDR2_DQM0
AE8
FRC_REXT
Y11
FRC_TESTPIN
Y19
ACKP/RLV3P/RED[3]
W26
ACKM/RLV3N/RED[2]
W25
A0P/RLV0P/RED[9]
U26
A0M/RLV0N/RED[8]
U25
A1P/RLV1P/RED[7]
U24
A1M/RLV1N/RED[6]
V26
A2P/RLV2P/RED[5]
V25
A2M/RLV2N/RED[4]
V24
A3P/RLV4P/RED[1]
W24
A3M/RLV4N/RED[0]
Y26
A4P/RLV5P/GREEN[9]
Y25
A4M/RLV5N/GREEN[8]
Y24
BCKP/TCON13/GREEN[1]
AC26
BCKM/TCON12/GREEN[0]
AC25
B0P/RLV6P/GREEN[7]
AA26
B0M/RLV6N/GREEN[6]
AA25
B1P/RLV7P/GREEN[5]
AA24
B1M/RLV7N/GREEN[4]
AB26
B2P/RLV8P/GREEN[3]
AB25
B2M/RLV8N/GREEN[2]
AB24
B3P/TCON11/BLUE[9]
AC24
B3M/TCON10/BLUE[8]
AD26
B4P/TCON9/BLUE[7]
AD25
B4M/TCON8/BLUE[6]
AD24
CCKP/LLV3P
AD23
CCKM/LLV3N
AE23
C0P/LLV0P/BLUE[5]
AE26
C0M/LLV0N/BLUE[4]
AE25
C1P/LLV1P/BLUE[3]
AF26
C1M/LLV1N/BLUE[2]
AF25
C2P/LLV2P/BLUE[1]
AE24
C2M/LLV2N/BLUE[0]
AF24
C3P/LLV4P
AF23
C3M/LLV4N
AD22
C4P/LLV5P
AE22
C4M/LLV5N
AF22
DCKP/TCON5
AD19
DCKM/TCON4
AE19
D0P/LLV6P
AD21
D0M/LLV6N
AE21
D1P/LLV7P
AF21
D1M/LLV7N
AD20
D2P/LLV8P
AE20
D2M/LLV8N
AF20
D3P/TCON3
AF19
D3M/TCON2
AD18
D4P/TCON1
AE18
D4M/TCON0
AF18
GPIO0/TCON15/HSYNC/VDD_ODD
AB22
GPIO1/TCON14/VSYNC/VDD_EVEN
AB23
GPIO2/TCON7/LDE/GCLK4
AC23
GPIO3/TCON6/LCK/GCLK2
AC22
FRC_GPIO0/UART_RX
AB16
FRC_GPIO1
AA14
FRC_GPIO3
AC15
FRC_GPIO8
Y16
FRC_GPIO9/UART_TX
AC16
FRC_GPIO10
AC14
FRC_I2CM_DA
AA16
FRC_I2CM_CK
AA15
FRC_I2CS_DA
Y10
FRC_I2CS_CK
AA11
FRC_PWM0
AB15
FRC_PWM1
AB14
DDR3(FRC)
GP2_Saturn7M
Ver. 1.4
3’d5 : boot from internal SRAM
3’d6 : boot from EEPROM
3’d7 : boot form SPI flash
CLose to Saturn7M IC
HIGH : I2C ADR = B8
LOW : I2C ADR = B4
(FRC_CONF1,FRC_PWM1, FRC_PWM0)
DDR3 1.5V By CAP - Place these Caps near Memory
CLose to DDR3
<U3 CHIP Config>
Close to DDR Power Pin
(FRC_CONF0)
3
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 42LE5300
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