THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR3_A[3]
DDR3_A[2]
DDR3_A[7]
DDR3_DQU[0]
DDR3_A[11]
DDR3_A[10]
DDR3_DQU[5]
DDR3_DQL[6]
DDR3_A[4]
DDR3_DQL[4]
DDR3_A[12]
DDR3_DQU[7]
DDR3_A[1]
DDR3_DQU[3]
DDR3_DQL[0]
DDR3_DQU[2]
DDR3_A[0]
DDR3_DQU[1]
DDR3_DQU[4]
DDR3_A[8]
DDR3_DQL[2]
DDR3_A[13]
DDR3_A[9]
DDR3_DQL[1]
DDR3_DQL[5]
DDR3_DQL[7]
DDR3_A[6]
DDR3_DQU[6]
DDR3_DQL[3]
DDR3_A[5]
DDR3_DQSU
FRC_MCLK
DDR3_CASB
R9702
1K
1%
DDR3_RASB
FRC_A[6]
FRC_A[2]
DDR3_DQSU
FRC_DQU[2]
FRC_DQL[3]
DDR3_MCKB
R9704
240
1%
FRC_A[5]
DDR3_CKE
DDR3_MCK
DDR3_DMU
R9712
22
C9714
0.01uF
50V
DDR3_A[13]
C9701
0.1uF
DDR3_DQL[1]
FRC_DQU[7]
AR9700
22
FRC_DQL[2]
FRC_BA2
FRC_CKE
DDR3_CASB
C9708
0.1uF
FRC_DQL[0]
DDR3_A[1]
DDR3_RESETB
FRC_A[13]
DDR3_A[10]
R9718
22
C9709
0.1uF
AR9707
22
C9702
0.1uF
16V
FRC_A[4]
AR9706
22
DDR3_DQL[6]
FRC_A[12]
+1.5V_FRC_DDR
DDR3_DQSLB
DDR3_DQU[1]
MVREFDQ
C9712
0.1uF
R9717
22
DDR3_A[2]
FRC_ODT
R9709
22
DDR3_WEB
DDR3_A[0-13]
DDR3_DQL[4]
DDR3_DQU[2]
C9713
0.1uF
DDR3_DQU[0-7]
DDR3_BA1
DDR3_BA1
R9703
1K
1%
DDR3_CKE
DDR3_DQL[7]
FRC_DQL[5]
AR9702
22
R9710
22
C9706
0.1uF
DDR3_DQL[2]
DDR3_A[8]
R9713
22
FRC_DQL[6]
FRC_DML
FRC_A[1]
DDR3_BA2
DDR3_DQL[0]
DDR3_MCKB
DDR3_DQU[4]
DDR3_BA2
DDR3_BA0
+1.5V_FRC_DDR
DDR3_DQSL
DDR3_MCK
C9704
0.1uF
DDR3_MCKB
FRC_WEB
FRC_DQL[1]
FRC_A[8]
DDR3_DQU[0]
DDR3_A[0]
FRC_DQU[0]
DDR3_DQU[3]
C9700
0.1uF
FRC_DQU[3]
FRC_DQU[6]
FRC_DQSL
AR9703
22
FRC_A[7]
FRC_DQL[4]
DDR3_DQL[0-7]
DDR3_DMU
AR9704
22
R9720
22
AR9705
22
C9705
0.1uF
DDR3_DQSUB
DDR3_DQU[6]
FRC_DQSUB
R9719
22
FRC_DMU
DDR3_A[7]
DDR3_A[4]
R9707
56
DDR3_DQSL
+1.5V_FRC_DDR
C9711
0.1uF
DDR3_DQU[5]
C9703
22uF
10V
R9711
22
DDR3_DQL[3]
DDR3_BA0
DDR3_DQL[5]
FRC_A[3]
AR9708
22
DDR3_DQSUB
DDR3_RASB
FRC_A[10]
MVREFCA
DDR3_DQU[7]
R9715
22
DDR3_A[6]
FRC_DQU[4]
R9700
1K
1%
R9701
1K
1%
FRC_BA1
+1.5V_FRC_DDR
FRC_DQSU
DDR3_DML
FRC_CASB
FRC_MCLKB
FRC_DQL[7]
R9705
150
OPT
DDR3_A[9]
C9707
0.1uF
FRC_DQSLB
FRC_A[0]
DDR3_DQSLB
FRC_A[9]
R9708
56
DDR3_A[11]
FRC_A[11]
DDR3_DML
DDR3_ODT
DDR3_WEB
R9714
22
MVREFDQ
+1.5V_FRC_DDR
FRC_RASB
FRC_BA0
+1.5V_FRC_DDR
DDR3_ODT
R9716
22
DDR3_A[12]
C9710
0.1uF
FRC_DQU[1]
DDR3_MCK
DDR3_RESETB
FRC_DQU[5]
FRC_DDR3_RESETB
DDR3_A[5]
MVREFCA
AR9701
22
DDR3_A[3]
R9706
510
H5TQ1G63EFR-PBC
IC9700
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
NC_7
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
URSA DDR3
53
LG1152 A0
55
2011. 02 .16
Place the serail damping resistors
in the middle of DRAM pattern
Close to DDR Pin
Place Close to DDR Pin
Place Close to DDR Pin
DDR3 1.5V De-Cap Place near Memory
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Summary of Contents for 42GA6400
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