LG 32LX30*C, Service Manual

Page: 22 / 73

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
MAIN3_DDR
2014/06/13
12
L14_CA_M1A
A-MA13
A-MA14
A-MA7
A-MA10
A-MA1
A-MA8
A-MA3
A-MA0
A-MA4
A-MA6
A-MA11
A-MA9
A-MA5
A-MA2
A-MA12
A-MBA0
A-MBA1
A-MBA2
A-MCKE
A-MCK
A-MCKB
A-MCASB
A-MWEB
A-MRASB
A-MODT
A-MRESETB
A-MDMU
A-MDML
A-MDQSU
A-MDQSUB
A-MDQSL
A-MDQSLB
A-MDQL4
A-MDQL0
A-MDQL3
A-MDQL7
A-MDQL5
A-MDQL2
A-MDQL6
A-MDQL1
A-MDQU1
A-MDQU3
A-MDQU0
A-MDQU4
A-MDQU5
A-MDQU2
A-MDQU6
A-MDQU7
R1109
240
1%
A/B_DDR3_CS
IC101-*1
LGE2133(128M)
M1A_128M_UO4
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
IC101
LGE2134(256M)
M1A_256M_UO4
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
IC101-*2
LGE2136(256M)
M1A_2
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
IC101-*3
LGE2135(128M)
M1A_1
B_DDR3_A[0]
E11
B_DDR3_A[1]
F12
B_DDR3_A[2]
D10
B_DDR3_A[3]
B10
B_DDR3_A[4]
E15
B_DDR3_A[5]
B11
B_DDR3_A[6]
F14
B_DDR3_A[7]
C11
B_DDR3_A[8]
D14
B_DDR3_A[9]
A12
B_DDR3_A[10]
F16
B_DDR3_A[11]
D13
B_DDR3_A[12]
D15
B_DDR3_A[13]
C12
B_DDR3_A[14]
E13
B_DDR3_BA[0]
A9
B_DDR3_BA[1]
D16
B_DDR3_BA[2]
A10
B_DDR3_MCLK
C13
B_DDR3_MCLKZ
B13
B_DDR3_MCLKE
E17
B_DDR3_ODT
B8
B_DDR3_RASZ
C8
B_DDR3_CASZ
B9
B_DDR3_WEZ
D11
B_RESET
F10
B_DDR3_CS0
D12
B_DDR3_DQSL
A19
B_DDR3_DQSU
B18
B_DDR3_DQML
C16
B_DDR3_DQMU
D21
B_DDR3_DQSBL
C18
B_DDR3_DQSBU
C17
B_DDR3_DQL[0]
A20
B_DDR3_DQL[1]
A16
B_DDR3_DQL[2]
C19
B_DDR3_DQL[3]
C15
B_DDR3_DQL[4]
C20
B_DDR3_DQL[5]
C14
B_DDR3_DQL[6]
B21
B_DDR3_DQL[7]
B15
B_DDR3_DQU[0]
F18
B_DDR3_DQU[1]
D19
B_DDR3_DQU[2]
D17
B_DDR3_DQU[3]
E21
B_DDR3_DQU[4]
E19
B_DDR3_DQU[5]
D20
B_DDR3_DQU[6]
D18
B_DDR3_DQU[7]
F20
ZQ
E9
A-MA13
A-MBA1
A-MDQL4
A-MDQU5
A-MA9
A-MDML
A-MDQL1
A-MA3
A-MWEB
A-MA14
A-MBA2
A-MDQL0
A-MDQU2
A-MA5
A-MDQSU
A-MDQU1
A-MA0
A-MRASB
A-MDQL7
A-MA7
A/B_DDR3_CS
A-MCKE
A-MDQL3
A-MDQU6
A-MA2
A-MDQSUB
A-MDQU3
A-MA4
A-MODT
A-MDQL5
A-MA10
A-MCK
A-MDQU7
A-MA12
A-MDQSL
A-MDQU0
A-MA6
A-MRESETB
A-MDQL2
A-MA1
A-MCKB
A-MBA0
A-MDQSLB
A-MDQU4
A-MA11
A-MDMU
A-MDQL6
A-MA8
A-MCASB
Copyright
ⓒ
2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only