LG 32LD650, Service Manual

Page: 44 / 52

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
2009.09.11
URSA3 (NO L.D.)
COMMON
90
FRC_DQL[3]
FRC_A[7]
FRC_DQU[1]
FRC_A[10]
FRC_A[8]
FRC_A[9]
FRC_A[11]
FRC_DQL[2]
FRC_DQL[0]
FRC_DQL[4]
FRC_DQL[6]
FRC_DQU[3]
FRC_DQL[1]
FRC_DQL[5]
FRC_DQU[0]
FRC_DQU[2]
FRC_DQU[5]
FRC_A[0]
FRC_DQU[4]
FRC_A[1]
FRC_A[2]
FRC_A[3]
FRC_A[12]
FRC_DQU[6]
FRC_A[6]
FRC_A[4]
FRC_DQL[7]
FRC_DQU[7]
FRC_A[5]
FRC_DQSL
+1.26V_MEMC
LVDS_TX_1_DATA1_N
RXD1-
C9033
0.1uF
LVDS_TX_0_CLK_P
FRC_WEB
FRC_CONF0
LVDS_TX_1_DATA2_N
RXD4-
AVDD_DDR
LVDS_TX_0_DATA2_P
R9044
1K
OPT
L9001
CIC21J501NE
AVDD_LVDS
RXA1+
LVDS_TX_0_DATA0_P
FRC_CONF0
FRC_SPI_DI
C9004
10uF
L9000
CIC21J501NE
FRC_BA2
C9018
0.1uF
RXB3-
L9006
CIC21J501NE
FRC_CASB
LVDS_TX_1_DATA4_N
FRC_MCLK
C9015
0.1uF
LVDS_TX_1_DATA0_N
RXB2+
LVDS_TX_0_DATA1_N
FRC_SPI_CZ
R9006 10
R9024
100
FRC_SPI_CK
RXCCK+
LVDS_TX_0_CLK_N
RXD2-
AVDD
C9011
0.1uF
R9045
1K
C9008
10uF
C9009
0.1uF
FRC_PWM1
FRC_DQSLB
RXA0+
C9013
0.1uF
FRC_A[0-12]
+3.3V_MEMC
RXB1-
LVDS_TX_1_DATA3_N
R9029
1M
R9011 100
RXA1-
GVDD_EVEN
C9029
0.1uF
RXA2+
RXB2-
AVDD_DDR
RXB3+
RXBCK+
R9021
100
FRC_BA1
RXA3-
R9025
100
R9032
100
GVDD_ODD
R9020
100
C9016
0.1uF
FRC_CONF0
FRC_RASB
C9025
10uF
RXD4+
RXB0-
R9019
100
RXA0-
AVDD_LVDS
LVDS_TX_1_DATA1_P
FRC_DQU[0-7]
R9037 0
MINI_LVDS
FRC_PWM0
RXC4+
FRC_CKE
FRC_DQSUB
AVDD
R9051
1K
OPT
C9027
0.1uF
FRC_SPI_DO
R9038
100
LD_SCAN
FRC_PWM0
RXA4-
R9014
100
RXA4+
RXBCK-
+3.3V_MEMC
FRC_SPI_CZ
+3.3V_MEMC
AVDD_PLL
LVDS_TX_1_CLK_N
FRC_MCLKB
C9024
10uF
LVDS_TX_1_CLK_P
RXDCK+
RXDCK-
C9010
0.1uF
C9035
0.1uF
LVDS_TX_0_DATA4_N
FRC_CONF1
C9017
0.1uF
C9030
0.1uF
R9027
100
RXA3+
R9039
100
LD_SCAN
LVDS_TX_1_DATA2_P
RXD3+
C9006
10uF
FRC_DQSU
FRC_BA0
R9049
1K
OPT
FRC_CONF1
RXC3-
C9014
0.1uF
RXCCK-
FRC_PWM0
R9016
100
FRC_DML
FRC_PWM1
R9030
0
URSA3
LVDS_TX_1_DATA0_P
RXB0+
RXD0-
RXC1-
LVDS_TX_0_DATA4_P LVDS_TX_0_DATA2_N
C9021
0.1uF
+1.5V_MEMC
R9018
100
AVDD_PLL
R9015
100
GCLK4
C9034
0.1uF
R9047
1K
OPT
R9022
100
LVDS_TX_0_DATA3_P
FRC_SPI_DO
RXD3-
R9017
100
RXC2-
RXB1+
R9040
0
C9031
0.1uF
C9026
0.1uF
RXC0+
C9005
0.1uF
R9026
100
+3.3V_MEMC
FRC_DDR3_RESETB
GCLK2
VDDP
C9012
0.1uF
VDDC
LVDS_TX_0_DATA0_N
RXC1+
R9005 10
R9041
820
RXD1+
RXA2-
RXACK+
AVDD_MEMPLL
LVDS_TX_0_DATA1_P
LVDS_TX_1_DATA4_P
RXB4-
C9007
10uF
FRC_RESET
FRC_DMU
SCAN_BLK2
AVDD_MEMPLL
FRC_SPI_DI
R9048
1K
FRC_SPI_CK
R9028
100
RXD2+
L9002
CIC21J501NE
R9012 100
H_CONV
C
9
0
2
8
0
.
1
u
F
FRC_PWM1
RXC3+
+3.3V_MEMC
RXC2+
FRC_DQL[0-7]
R9000 10
C9032
0.1uF
VDDC
RXACK-
R9023
100
LVDS_TX_1_DATA3_P
RXC4-
C9000
10uF
VDDP
L9005
CIC21J501NE
R9013
100
R9002 10K
DPM_A
L9003
CIC21J501NE
R9001 10
C9023
0.1uF
RXB4+
C9022
0.1uF
LVDS_TX_0_DATA3_N
R9050
1K
+3.3V_MEMC
FRC_ODT
SCAN_BLK1/OPC_OUT
L9004
CIC21J501NE
RXD0+
RXC0-
R9031
100
+3.3V_MEMC
R9046
1K
V_SYNC
R9043
0
OPT
SDA1_3.3V
SCL1_3.3V
URSA3_SDA
URSA3_SCL
URSA3_SCL
URSA3_SDA
URSA3_SDA
URSA3_SCL
X9000
12MHz
P9000
12505WS-04A00
1
2
3
4
5
L9007
CIC21J501NE
C9036
10uF
C9037
0.1uF
VDDC
+3.3V_MEMC
SW9000
JTP-1127WEM
1 2
4 3
R9003 22
R9004 22
+3.3V_MEMC
R9007
22
R9008 22
SDA3_3.3V
SCL3_3.3V
C9020
10uF
C9003
10uF
C9019
10uF
C9001
10uF
C9002
10uF
R9034 4.7K
URSA3_NON_MIRROR
R9033 4.7K
URSA3_MIRROR
R9035 4.7K
URSA3_MINI_LVDS
R9036 4.7K
URSA3_LVDS
R9010 22
OPT
R9009 22
OPT
IC9000
MX25L4005CM2I-12G
URSA3_FLASH_MACRONIX
EAN61009401
3
WP#
2
SO
4
GND
1
CS#
5
SI
6
SCLK
7
HOLD#
8
VCC
IC9000-*2
W25X40VSSIG
URSA3_FLASH_WINBOND_OLD
EAN35097301
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
LGE7378A[FRC_TCON_URSA3]
IC9001
URSA3
DDR3_A0/DDR2_NC
E2
DDR3_A1/DDR2_A6
U6
DDR3_A2/DDR2_A7
E3
DDR3_A3/DDR2_A1
G2
DDR3_A4/DDR2_CASZ
R4
DDR3_A5/DDR2_A10
G1
DDR3_A6/DDR2_A0
U5
DDR3_A7/DDR2_A5
F3
DDR3_A8/DDR2_A2
T5
DDR3_A9/DDR2_A9
F1
DDR3_A10/DDR2_A11
R6
DDR3_A11/DDR2_A4
R5
DDR3_A12/DDR2_A8
T6
DDR3_BA0/DDR2_BA2
G3
DDR3_BA1/DDR2_ODT
U4
DDR3_BA2/DDR2_A12
E1
DDR3_MCLK/DDR2_MCLK
U1
DDR3_MCLKZ/DDR2_MCLKZ
U2
DDR3_CKE/DDR2_RASZ
T4
DDR3_ODT/DDR2_BA1
H2
DDR3_RASZ/DDR2_WEZ
J1
DDR3_CASZ/DDR2_CKE
H3
DDR3_WEZ/DDR2_BA0
H1
DDR3_RESET/DDR2_A3
F2
DDR2_DQS0/DDR3_DQS0
M3
DDR2_DQS1/DDR3_DQS1
N2
DDR2_DQSB0/DDR3_DQSB0
N1
DDR2_DQSB1/DDR3_DQSB1
N3
DDR2_DQ7/DDR3_DQM0
R2
DDR2_DQ11/DDR3_DQM1
K3
DDR2_DQ6/DDR3_DQ0
K2
DDR2_DQ0/DDR3_DQ1
R3
DDR2_DQ1/DDR3_DQ2
K1
DDR2_DQ2/DDR3_DQ3
T1
DDR2_DQ4/DDR3_DQ4
J2
DDR2_NC/DDR3_DQ5
T3
DDR2_DQ3/DDR3_DQ6
J3
DDR2_DQ5/DDR3_DQ7
T2
DDR2_DQ8/DDR3_DQ8
P2
DDR2_DQ14/DDR3_DQ9
L3
DDR2_DQ13/DDR3_DQ10
R1
DDR2_DQ12/DDR3_DQ11
L1
DDR2_DQ15/DDR3_DQ12
P1
DDR2_DQ9/DDR3_DQ13
L2
DDR2_DQ10/DDR3_DQ14
P3
DDR2_DQM1/DDR3_DQ15
M1
DDR2_DQM0/DDR3_NC
M2
I2CM_SDA
C9
I2CM_SCL
D9
I2CM_SDA2_L
P7
I2CM_SCL2_L
N8
I2CM_SDA2_R
P9
I2CM_SCL2_R
N10
AVDD_1
F8
AVDD_2
F9
AVDD_DDR_1
L5
AVDD_DDR_2
L6
AVDD_DDR_3
L7
AVDD_DDR_4
L8
AVDD_DDR_5
M7
AVDD_DDR_6
M8
AVDD_LVDS_1
G12
AVDD_LVDS_2
H12
AVDD_LVDS_3
J12
AVDD_LVDS_4
K12
AVDD_MEMPLL
M6
AVDD_PLL_1
F11
AVDD_PLL_2
F12
DVDD_DDR[1.26V]
J5
VDD_EVEN
E16
VDD_ODD
E17
VDDC_1
F6
VDDC_2
F7
VDDC_3
G5
VDDC_4
G6
VDDC_5
G7
VDDC_6
H5
VDDC_7
H6
VDDC_8
J6
VDDP_1
G11
VDDP_2
K5
VDDP_3
K6
VDDP_4
M10
VDDP_5
M11
VSS_1
C10
VSS_2
C12
VSS_3
G8
VSS_4
G9
VSS_5
G10
VSS_6
H7
VSS_7
H8
VSS_8
H9
VSS_9
H10
VSS_10
H11
VSS_11
J4
VSS_12
J7
VSS_13
J8
VSS_14
J9
VSS_15
J10
VSS_16
J11
VSS_17
K7
VSS_18
K8
VSS_19
K9
VSS_20
K10
VSS_21
K11
VSS_22
L9
VSS_23
L10
VSS_24
L11
VSS_25
M9
VSS_26
N4
VSS_27
P6
A10
A10
A11
A11
A12
A12
B10
B10
B11
B11
B12
B12
C11
C11
D11
D11
TESTPIN
L13
VB1_TEST
F10
A0P/RV0+
B14
A0M/RV0-
A14
A1P/RV1+
C14
A1M/RLV1-
C15
A2P/RV2+
A15
A2M/RV2-
B15
ACKP/R3+
B16
ACKM/RV3-
A16
A3P/RV4+
A17
A3M/RV4-
B17
A4P/RV5+
C16
A4M/RV5-
C17
B0P/RV6+
D16
B0M/RV6-
D17
B1P/RV7+
D15
B1M/RV7-
E15
B2P/RV8+
F16
B2M/RV8-
F17
BCKP/WPWM
F15
BCKM/OPT_P
G15
B3P/OPT_N
G17
B3M/FLK
G16
B4P/GCLK6
H16
B4M/GLCK5
H17
C0P/LV0+
H15
C0M/LV0-
J15
C1P/LV1+
J17
C1M/LV1-
J16
C2P/LV2+
K16
C2M/LV2-
K17
CCKP/LV3+
K15
CCKM/LV3-
L15
C3P/LV4+
L17
C3M/LV4-
L16
C4P/LV5+
M16
C4M/LV5-
M17
D0P/LV6+
M15
D0M/LV6-
N15
D1P/LV7+
N17
D1M/LV7-
N16
D2P/LV8+
P15
D2M/LV8-
R15
DCKP/GOE
R17
DCKM/GSC/GCLK3
R16
D3P/GSP_R
T16
D3M/GSP
T17
D4P/SOE
T15
D4M/POL
U17
GCLK4
P16
GCLK2
P17
I2CS_SDA
D1
I2CS_SCL
D2
PWM0
P14
PWM1
R14
LPLL_FBCLK
B13
LPLL_OUTCLK
U16
LPLL_REFIN
A13
RECKP
A2
RECKN
B2
RE0P
A4
RE0N
B4
RE1P
C3
RE1N
C4
RE2P
B3
RE2N
A3
RE3P
C1
RE3N
C2
RE4P
B1
RE4N
A1
ROCKP
A6
ROCKN
B6
RO0P
A8
RO0N
B8
RO1P
C7
RO1N
C8
RO2P
B7
RO2N
A7
RO3P
C5
RO3N
C6
RO4P
B5
RO4N
A5
XTALO
A9
XTALI
B9
GPIO[0]
K14
GPIO[1]
J13
GPIO[2]
H14
GPIO[3]
G13
GPIO[4]
F14
GPIO[5]
E13
GPIO[8]
D3
GPIO[9]
D4
GPIO[10]
E4
GPIO[12]
D5
GPIO[13]
D7
GPIO[14]
F4
M_S_PIF_CLK_1
R7
M_S_PIF_CLK_2
U8
M_S_PIF_CS
U7
M_S_PIF_DA1
T8
M_S_PIF_FC
T7
S_M_PIF_CLK
U14
S_M_PIF_CS
U15
S_M_PIF_DA0
R13
S_M_PIF_DA1
T13
S_M_PIF_FC
T14
LTD_CLK_L
T10
LTD_CLK_R
T11
LTD_DA0_L
R10
LTD_DA0_R
U11
LTD_DA1_L
R9
LTD_DA1_R
U12
LTD_DE_L
U10
LTD_DE_R
R11
OP_SYNC_L
U9
OP_SYNC_R
R12
PLL_LOCK_L
T9
PLL_LOCK_R
T12
SOFT_RST_L
R8
SOFT_RST_R
U13
SPI_CK
P13
SPI_CZ
N14
SPI_DI
N12
SPI_DO
N13
RESET
M14
REXT
C13
C9038
22pF
C9039
22pF
IC9000-*1
W25X40BVSSIG
URSA3_FLASH_WINBOND_NEW
3
WP
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD
8
VCC
R9052 4.7K
URSA3_NON_GIP
R9053 4.7K
URSA3_GIP
R9055 4.7K
URSA3_SCANNING_OFF
R9057 4.7K
URSA3_LOCAL_DIMMING
R9054 4.7K
URSA3_SCANNING_ON
R9056 4.7K
URSA3_NON_LOCAL_DIMMING
R9042
100
Serial Flash
I2C ADR: GPIO1: HI:B8 LOW:B4
CHIP_CONF: {GPIO8, PWM1, PWM0}
CHIP_CONF= 3
d5: boot from internal SRAM
CHIP_CONF= 3 d6: boot from EEPROM
CHIP_CONF= 3 d7: boot from SPI Flash
Separate DVDD_DDR Power
SCAN_OFF
HIGH
K14 NON_MIRROR
NON_GIP
LD
LVDS
SCAN_ON
R9
LOW
U10
GIP
MINI_LVDS
R10
NON_LD
MIRROR
T10
FRC OPTION