Lauterbach XC800 Page 4 Manual Download

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XC800 Debugger | 4

1989-2021

Lauterbach GmbH

XC800 Debugger

Version 04-Nov-2021

Introduction

This document describes the processor specific settings and features for TRACE32-ICD for the
Infineon XC800 CPU family.

Please keep in mind that only the

Processor Architecture Manual

(the document you are reading at the

moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.

Brief Overview of Documents for New Users

Architecture-independent information:

•

“Debugger Basics - Training”

(training_debugger.pdf): Get familiar with the basic features of a

TRACE32 debugger.

•

“T32Start”

(app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.

•

“General Commands”

(general_ref_

<x>

.pdf): Alphabetic list of debug commands.

Architecture-specific information:

•

“Processor Architecture Manuals”

: These manuals describe commands that are specific for the

processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:

Choose

Help

menu >

Processor Architecture Manual

•

“OS Awareness Manuals”

(rtos_

<os>

.pdf): TRACE32 PowerView can be extended for operating

system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.

Summary of Contents for XC800

Page 1: ...MANUAL Release 09 2021 XC800 Debugger ...

Page 2: ...p Breakpoints 10 CPU specific SYStem Settings and Restrictions 11 SYStem state Open system window 11 SYStem CONFIG Configure debugger according to target topology 11 Daisy Chain Example 14 TapStates 15 SYStem CONFIG CORE Assign core to TRACE32 instance 16 SYStem CONFIG state Display target configuration 17 SYStem CPU Select CPU 17 SYStem MemAccess Select memory access mode 18 SYStem Mode Establish...

Page 3: ...N bit 22 SYStem JtagClock Define JTAG clock 23 TrOnchip Commands 24 TrOnchip CONVert Adjust range breakpoint in on chip resource 24 TrOnchip RESet Set on chip trigger to default state 24 TrOnchip state Display on chip trigger window 24 TrOnchip VarCONVert Adjust complex breakpoint in on chip resource 25 OCDS1 Connector 26 Memory Classes 28 ...

Page 4: ...sics Training training_debugger pdf Get familiar with the basic features of a TRACE32 debugger T32Start app_t32start pdf T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger T32Start is only available for Windows General Commands general_ref_ x pdf Alphabetic list of debug commands Architecture specific information Processor Architecture Manuals...

Page 5: ... the target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 Connect the Debug Cable to the target 6 Switch the target power ON 7 Configure your debugger e g via a start up script Power down 1 Switch off the target power 2 Disconnect the Debug Cable from the ...

Page 6: ...bcommands of MAP to define inaccessible memory areas Bus errors can be removed by executing SYStem Up Make sure that there isn t any TRACE32 window open which accesses to a inaccessible memory that is not masked out otherwise the bus error can occur again 7 Enter debug mode This command resets the CPU and enters debug mode After this command is executed it is possible to access memory and register...

Page 7: ...shown below b Select the ICD device prompt WinCLEAR Clear all windows SYStem CPU XC888 Select CPU SYStem Up Reset the target and enter debug mode Data LOAD OMF MYPROG VERFY Load the application verify the process Go main Run and break at main Data List Open source window Register view SpotLight Open register window Var Local Open window with local variables ...

Page 8: ... The debugger controls the processor reset and use the RESET line to reset the CPU on every SYStem Up Therefore no external R C combination or external reset controller is allowed There is logic added to the JTAG state machine By default the debugger supports only one processor in one JTAG chain If the processor is only one member of a JTAG chain the debugger has to be informed about the target JT...

Page 9: ...nfiguration The processor type must be selected by the SYStem CPU command before issuing any other target related commands POWER DEBUG USB INTERFACE USB 3 POWER DEBUG INTERFACE USB 3 PC or Workstation USB Cable Target Debug Connector Debug Cable ...

Page 10: ... the on chip breakpoints for the XC800 On chip breakpoints Total amount of available on chip breakpoints Instruction breakpoints Number of on chip breakpoints that can be used to set Program breakpoints into ROM FLASH EEPROM Read Write breakpoints Number of on chip breakpoints that can be used as Read or Write breakpoints Data breakpoint Number of on chip data breakpoints that can be used to stop ...

Page 11: ...e Manual in case you want to know the effect of these commands on a debugger The four parameters IRPRE IRPOST DRPRE DRPOST are required to inform the debugger about the TAP controller position in the JTAG chain if there is more than one core in the JTAG chain e g Arm DSP The information is required before the debugger can be activated e g by a SYStem Up See Daisy chain Example For some CPU selecti...

Page 12: ...er If each core in the system contributes only one TAP to the JTAG chain DRPRE is the number of cores between the core of interest and the TDO signal of the debugger DRPOST default 0 number of TAPs in the JTAG chain between the TDI signal of the debugger and the core of interest If each core in the system contributes only one TAP to the JTAG chain DRPOST is the number of cores between the TDI sign...

Page 13: ...rt access Then other debuggers can access the port JTAG This option must be used if the JTAG line of multiple debug boxes are connected by a JTAG joiner adapter to access a single JTAG chain Slave default OFF If more than one debugger share the same debug port all except one must have this option active JTAG Only one debugger the master is allowed to control the signals nTRST and nSRST nRESET ...

Page 14: ...tion register length of Core A 3 bit Core B 5 bit Core D 6 bit SYStem CONFIG IRPRE 6 IR Core D SYStem CONFIG IRPOST 8 IR Core A B SYStem CONFIG DRPRE 1 DR Core D SYStem CONFIG DRPOST 2 DR Core A B SYStem CONFIG CORE 0 1 Target Core C is Core 0 in Chip 1 Core A Core B Core C Core D TDO TDI Chip 0 Chip 1 ...

Page 15: ...rbach GmbH TapStates 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15 Test Logic Reset ...

Page 16: ... are configured with different chip_index values Therefore you have to assign the core_index and the chip_index for every core Usually the debugger does not need further information to access cores in non generic chips once the setup is correct Generic Chips Generic chips can accommodate an arbitrary amount of sub cores The debugger still needs information how to connect to the individual cores e ...

Page 17: ...ional SYStem CONFIG commands for settings that are not included in the SYStem CONFIG state window SYStem CPU Select CPU Selects the processor type Format SYStem CONFIG state tab tab DebugPort Jtag tab Opens the SYStem CONFIG state window on the specified tab DebugPort JTAG DebugPort Lets you configure the electrical properties of the debug connection such as the communication protocol or the used ...

Page 18: ...CPU deprecated A run time memory access is made without CPU intervention while the program is running This is only possible on the instruction set simulator StopAndGo Temporarily halts the core s to perform the memory access Each stop takes some time depending on the speed of the JTAG port the number of the assigned cores and the operations that should be performed ...

Page 19: ...e debugger The state of the CPU remains unchanged The JTAG port is tri stated Go Resets the target and enables the debugger and start the program execution Program execution can be stopped by the break command or if any break condition occurs Attach User program remains running no reset and the debug mode is activated After this command the user program can be stopped with the break command or if ...

Page 20: ...mbH If the system is locked no access to the JTAG port will be performed by the debugger While locked the JTAG connector of the debugger is tristated The intention of the SYStem LOCK command is for example to give JTAG access to another tool ...

Page 21: ...mask bits are restored to the value before the step SYStem Option IMASKHLL Disable interrupts while HLL single stepping Default OFF If enabled the interrupt mask bits of the CPU will be set during HLL single step operations The interrupt routine is not executed during single step operations After single step the interrupt mask bits are restored to SYStem Option LittleEndian Treat memory as little ...

Page 22: ...5h is re used for this instruction The functionality of the 0A5h opcode is determined by the bit TRAP_EN in the Extended Operations EO register usually EO 4 When TRAP_EN 1 set 0A5h means TRAP When TRAP_EN 0 reset 0A5h means MOVC DPTR A This conflicts with the operation of software breakpoints Software breakpoints are set by replacing an instruction with a TRAP instruction When the processor stops ...

Page 23: ... data transfer Therefore we recommend to use the default setting if possible When the debugger is not working correctly e g memory is flickering decrease the JtagClock Format SYStem JtagClock frequency RTCK ARTCK frequency CTCK frequency CRTCK frequency SYStem BdmClock frequency deprecated frequency 6 kHz 80 MHz 1250000 2500000 5000000 10000000 frequency The debugger cannot select all frequencies ...

Page 24: ...et on chip trigger to default state Sets the TrOnchip settings and trigger module to the default settings TrOnchip state Display on chip trigger window Opens the TrOnchip state window Format TrOnchip CONVert ON OFF deprecated Use Break CONFIG InexactAddress instead TrOnchip CONVert ON Break Set 0x1000 0x17ff Write Break Set 0x1001 0x17ff Write TrOnchip CONVert OFF Break Set 0x1000 0x17ff Write Bre...

Page 25: ...akpoint to a complex variable the on chip break resources of the CPU may be not powerful enough to cover the whole structure If the option TrOnchip VarCONVert is set to ON the breakpoint will automatically be converted into a single address breakpoint This is the default setting Otherwise an error message is generated Format TrOnchip VarCONVert ON OFF deprecated Use Break CONFIG VarConvert instead...

Page 26: ...hat means the output voltage of the debugger signals TMS TDI TCLK TRST BRKIN depends directly on VCCS VCCS can be 2 25 5 5 V The output buffer takes about 2 mA RESET is controlled by an open drain driver An external watchdog must be switched off if the In Circuit Debugger is used BRKIN and BRKOUT must be configured in MCBS Multi Core Break Switch for before they can be used VIHmin 2 0 V VILmax 0 8...

Page 27: ...evice in the chain 4 6 12 GND System Ground Plan Connect to digital ground 7 TDI Test Data In No other devices in the JTAG chain are allowed between the Debug Cable and the XC800 8 RESET Reset Connect to PORST and connect PORST to VCC via a 10 K pull up resistor Do not connect to TRST 9 TRST Test Reset Connect to TRST if available Do not connect to PORST 10 BRKOUT Break out None 11 TCLK Test clock...

Page 28: ...n the memory class D represent the Special Function Registers SFR standard The Special Function Registers standard mapped and paged can be accessed in the peripherie window XRAM can be read written as program memory or external memory Memory Class Description P Code space program X External data space including XRAM I Internal RAM Indirect Address D Special Function Registers non mapped Internal R...

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