Lauterbach TRACE32-ICD, Manual, Page: 59 / 65

PPC600 Family Debugger | 59
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CPU specific BenchMarkCounter Commands
The BenchMarkCounter features are based on the core’s performance monitor, accessed through the
performance monitor registers (PMR). Only processors with
e300c3 and e300c4 cores have performance
monitor registers:
• MPC830X
• MPC831X
• MPC512X
PMR access is only possible while the core is halted. For other processors, the BenchMarkCounter features
are not available.
BMC.<counter>.FREEZE Freeze counter in certain core states
Halts the selected performance counter if one or more of the enabled states (i.e. states set to ON) match the
current state of the core. If contradicting states are enabled (e.g. SUPERVISOR and USER), the counter will
be permanently frozen. The table below explains the meaning of the individual states.
NOTE:
• For information about architecture-independent BMC commands, refer to
“BMC” (general_ref_b.pdf).
• For information about architecture-specific BMC commands, see
command descriptions below.
• Events can be assigned to the BMC commands BMC.<counter>.EVENT
<event> and BMC.<counter>.RATIO X/<counter n> .
For descriptions of available events, see Freescale’s e300 core reference
manual (Table 11-9, Performance Monitor Event Selection).
Format: BMC. <counter> .FREEZE <state> [ ON | OFF ]
<state> : USER | SUPERVISOR | MASKSET | MASKCLEAR
<state> Dependency in core
USER Counter frozen if MSR[PR]==1
SUPERVISOR Counter frozen if MSR[PR]==0
MASKSET Counter frozen if MSR[PMM]==1
MASKCLEAR Counter frozen if MSR[PMM]==0