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Lauterbach PowerTrace Serial User Manual Download Page 35

  PowerTrace Serial User´s Guide

 

    35     

  

©1989-2018 Lauterbach GmbH

Types of Trace Decoder Errors

One of the following errors may occur:

•

 Harderror

•

 Flowerror

•

 Fifofull

Harderror

There is no valid trace data. Possible reasons are:

•

Wrong lane order

•

Wrong endianness configuration (bit/byte/word/long)

•

Skipping wrong amount of bytes (CRC or not)

Please see 

Diagnosis Check List

.

Flowerror

The traced data is not consistent with the code in the target memories. Possible reasons are:

•

Memory contents have changed (e.g. self modifying code).

•

Wrong endianness configuration (bit/byte/word/long)

•

Skipping wrong amount of bytes at the end of each Aurora frame (CRC or not)

Please see 

Diagnosis Check List

.

Summary of Contents for PowerTrace Serial

Page 1: ...l 5 Adapter for AGBT LA 3556 8 Adapter for RH850 LA 3561 9 Adapter for Mini PCIe LA 3526 11 Adapter for PCIe Slot Card LA 3525 12 Configuration Switches 17 Configuration Guide 20 Software Installation 21 Recommendation for the Software Start 21 Recommendation for Power Down 21 Trace Port Utilization 22 HSSTP based Trace Port 22 Start up Script 23 Example 23 AGBT based Trace Port 27 Serial NEXUS ba...

Page 2: ...Accessory Sets 43 LA 3521 ACC PTSERIAL ETM 1 6 43 LA 1235 40pin Flex Cable 43 LA 2770 Mipi34 ARM20 Adapter 44 LA 2114 34pin Half Size Cable 44 LA 3522 ACC PTSERIAL ETM 7 8 45 LA 1239 80pin Flex Cable 45 Electrical Specification for PowerTrace Serial 46 Electrical Characteristics 46 Absolute Maximum Ratings 46 Switching Characteristics 46 Timing Characteristics 47 Maximum Lane Skew 47 Additional Da...

Page 3: ...or lane counts higher than four the PowerTrace Serial will be the preferred tool Higher speeds are always combined with higher demand on system design New interfaces require digging into new papers of peripheral components There is more work to do and higher potential of malfunction This User s Guide intends to flatten the path to a well working Gigabit trace setup Intended Audience This manual ca...

Page 4: ...llowing information and files to icrstp support lauterbach com Used start up configuration scripts List of all TRACE32 device adapters and cables A picture of your complete trace debug hardware setup if possible The complete text of the error messages you get AREA view Trace connector pinout board schematics and layout Is the problem lane speed or lane count dependent A screenshot of each lane sho...

Page 5: ...nsure correct positioning The connectors must be clean and without any damage 2 Connect the flex cable and if necessary the debug cable to Serial Port 0 or Serial Port 1 of the PowerTrace Serial Check the connector orientation of tool and target there are two 45 corners A and two 90 corners B The marker of pin 1 C of the plug is easy to miss but is located close to one 45 corner A For better illus...

Page 6: ...es are labeled to make the installation easier Serial Port 0 The debug cable can be connected to the PowerTrace Serial module or directly to the target depending on the target trace connector pin out Serial Port 1 The debug cable must be connected to the target directly or ...

Page 7: ...PowerTrace Serial User s Guide 7 1989 2018 Lauterbach GmbH requires an adapter to merge debug and trace signals to a single cable ...

Page 8: ... Function A AUTO26 debug connector B JTAG16 debug connector C Target connector D PowerTrace Serial connector for Serial Port 1 Both debug connectors AUTO26 A and the JTAG16 B hold the same debug signals coming from the target connector C Only one debug connector at the time must be used B A C D ...

Page 9: ... D PowerTrace Serial connector for Serial Port 1 Jumper Function X130 Set Connects pin 16 EVTI of the target connector to TRIGOUT of PowerTrace Serial Open EVTI not connected X131 Set Connects pin 18 EVTO of the target connector to TRIGIN of PowerTrace Serial Open EVTO not connected X132 DO NOT SET Pin 1 Connected to pin 34 of the target connector RESOUT Pin 2 GND B A C D ...

Page 10: ...en pin 14 of Auto26 is open Pin31 Set Connects pin 31 of the target connector to pin 22 BREQ of AUTO26 Open pin 22 of Auto26 is open Pin33 Set Connects pin 27 of the target connector to pin 24 BGNT of AUTO26 Open pin 24 of Auto26 is open Both debug connectors AUTO26 A or the JTAG14 B hold the same debug signals coming from the target connector C Only one debug connector must be used at the time Ju...

Page 11: ... Adapter for Mini PCIe LA 3526 The passive adapter card is used to adapt PC like targets with trace data coming via MiniPCIe connectors Insert the adapter carefully Connector Function A MiniPCIe edge connector B PowerTrace Serial connector for Serial Port 1 A B ...

Page 12: ...matic configuration mode or manual configuration mode for PCIe Gen1 2 and 3 The form factor follows the standard for PC slot in cards The card can be plugged into standard 16 lane slots 8 lane slots and in case of special open frame connectors also into 4 lane slots and 1 lane slots If necessary the metal plate can be removed The adapter will be shipped in auto configuration mode which will work f...

Page 13: ...eemphasis for groups of lanes RX and TX E Selector for adapter configuration mode for RX path F Selector for protocol specific behavior for RX path G Selector for termination style for RX path H Selector for adapter configuration mode for TX path J Selector for protocol specific behavior for RX path K Selector for termination style for TX path L Selector for EEPROM configuration M PCIe device pres...

Page 14: ...o target LED Function RX DONE On RX register configuration done Off RX register configuration in progress failed or target not powered TX DONE On TX register configuration done Off TX register configuration in progress failed or target not powered NOTE The adapter configuration of RX buffers and TX buffers is pipelined The TX configuration can only succeed if RX configuration was successful ...

Page 15: ...programming mode Open normal mode PRSNT Jumper Function PRSNT Set number of lanes regarding to the PCIe standard The target OS sometimes needs this information to configure the PCIe root complex correctly Don t leave the jumper open Select the next higher number of your lane count e g x4 in case of 2 lanes Set x1 select 1 lane Set x4 select 4 lanes Set x8 select 8 lanes RX Jumper Function SCL SEL ...

Page 16: ...CIe Gen1 2 Open Auto detection of driver parameter TX Jumper Function SCL SEL Must be set to 2 3 Set 1 2 SMB mode Set 2 3 Pin mode SDA SEL Must be set to 2 3 Set 1 2 SMB mode Set 2 3 Pin mode TXTERM Termination behavior during signal detection Default Open Open unlimited cyclic RX test Hi Z during test then 50 Set 1 2 limited cyclic RX test Hi Z during test then 50 Set 2 3 manual test with 50 term...

Page 17: ...utual group e g switch 1 3 parameter EQ0 Within a group only one switch must be on Driver settings for RX and TX will match in most cases EQ0 EQ1 dB at 1 5GHz dB at 2 5GHz dB at 4GHz dB at 6GHz Suggested for 1 100 100 2 5 3 5 3 8 3 1 FR4 and less than 5inch traces 2 010 100 3 8 5 4 6 7 6 7 FR4 5 10inch traces 3 000 100 5 0 7 0 8 4 8 4 FR4 10inch traces 4 001 100 5 9 8 0 9 3 9 1 FR4 15 20inch trace...

Page 18: ...4 4 19 8 24 2 24 7 13 100 001 14 4 20 5 26 4 28 0 14 010 001 16 0 22 2 27 8 29 2 15 000 001 17 6 24 4 30 2 30 9 16 001 001 18 7 25 8 31 6 31 9 else else Not allowed Equalizer configuration 1 is default DE0 DE1 Vp p DEM dB internal Vp p Suggested for 1 100 100 0 8 0 0 8 FR4 and less than 5inch 4mil traces 2 010 100 0 9 0 0 9 FR4 and less than 5inch 4mil traces 3 000 100 0 9 3 5 0 6 FR4 and 10inch 4...

Page 19: ...es 9 100 000 1 1 6 0 6 FR4 and 15inch 4mil traces 10 010 000 1 2 0 1 2 FR4 and less than 5inch 4mil traces 11 000 000 1 2 3 5 0 8 FR4 and 10inch 4mil traces 12 001 000 1 2 6 0 6 FR4 and 15inch 4mil traces 13 100 001 1 3 0 1 3 FR4 and less than 5inch 4mil traces 14 010 001 1 3 3 5 0 9 FR4 and 10inch 4mil traces 15 000 001 1 3 6 0 7 FR4 and 15inch 4mil traces 16 001 001 1 3 9 0 5 FR4 and 20inch 4mil...

Page 20: ...high high bandwidth reduction Start with the first configuration 1 and increase step by step 2 3 To verify the configuration the data eye scanner should be used Analyzer ShowFocusEye Always first disable the switches before you enable the next configuration Don t have more than one switch enabled within a group Changing the configuration must be done like this 100 current configuration 000 set tem...

Page 21: ...s to the target If there is no appropriate jack on your target you can also connect the debug cable to the debug port of Serial Port 0 if this port is planned to be used for ARM Mipi conform devices only Alternatively connect the debug cable to an additional converter PCB which splits debug and trace signals The converter PCB needs to be ordered separately at Lauterbach 6 Connect the Serial Port 0...

Page 22: ...on on the target side to configure the CPU to send trace information A common trace setup consists of the following parts TRACE32 start up Connection of system modules Establishing host connection Starting TRACE32 PowerView TRACE32 setup Debug and trace port connection CPU selection system mode Peripheral external buffer enable GPIO trace port PLL pin manager Trace logic base address filter Applic...

Page 23: ...device dependent TRACEPORT MsgBItEndian TRACEPORT MsgBYteEndian TRACEPORT MsgWOrdEndian TRACEPORT MsgLOngEndian Definition of skipping bytes is device dependent TRACEPORT StartsKiP TRACEPORT EndsKiP The need of a tool sourced reference clock is target dependent TRACEPORT RefCLocK Turn on the ETM with the command ETM ON B The target must be configured Set up the I O ports PHYs To find the required ...

Page 24: ...RTEXR5 SYStem Up Initialize system Select JTAG clock Select CPU type Start debugger TARGET SETUP Data Set SD 0x10000014 LE L 0a05f Data Set SD 0x10000008 LE LONG 20 SYStem Option BigEndian OFF Unlock target reg Set target frequency Set endianism PROGRAM SETUP Data LOAD ELF armle axf SPATH LPATH Register Set PC main Load example program Set program counter to program start ...

Page 25: ... ETM CORE 0 ETM PortMode CONTINUOUS ETM DataTrace Both ETM ON SYStem CONFIG TRACEPORT Type AURORA SYStem CONFIG TRACEPORT1 TraceSource TPIU TRACEPORT LaneSpeed 6000Mbps TRACEPORT LaneCount 4lane TRACEPORT MsgBItEndian BigEndian TRACEPORT EndsKiP 2 Assign Coresight ETM Base Address Funnel Base Address ETF Base Address TPIU Base Address ETR Base Address Assign core 0 Set the trace mode to Continuous...

Page 26: ...able Set Verify bond and alignment lengths Configure lane count C Train Serial Channel and Test ad 0x80001204 TIMEOUT 2s WHILE Analyzer ISCHANNELUP Data Set EAPB 0x80001200 LE LONG 0x00000000 Data Set EAPB 0x80001200 LE LONG 0x0000000C Data Set EAPB 0x80001200 LE LONG 0x0000000D WAIT CONV INTTOBOOL D long EAPB ad 0x4f 1s IF TIMEOUT Data Set EAPB 0x80001200 LE LONG 0x0000000F ELSE PRINT Failed to g...

Page 27: ...ifferent architectures Each architecture requires its own configuration on the target side to configure the target device to send trace information via PCIe A common trace setup consists of the following parts TRACE32 start up Connection of system modules Establishing host connection Starting TRACE32 PowerView TRACE32 setup Debug and trace port connection CPU selection system mode Trace logic base...

Page 28: ... A The following settings are required Configuration trace environment with the command SYStem CONFIG TRACEPORT Init analyzer with the command Analyzer Init B The target must be configured Set up the I O ports PHYs To find the required information refer to your CPU manual Set up the board buffers jumpers etc To find the required information refer to your target user guide Configure PCIe root compl...

Page 29: ... Go direct main A TRACE32 TRACE SETUP SYStem CONFIG TRACEPORT Type PCIE TRACEPORT PortType PCIE Analyzer Init B TARGET PCIe SETUP script DO setup_ls_pcie 0x03600000 0x5000000000 C TARGET TRACE SETUP script EtrAxiBase 0x5049000000 DO etr_utility cmm ETR1 set DAB EtrAxiBase DO etr_utility cmm ETR1 set RSZ 0x8 DO etr_utility cmm ETR1 set AXICTL 0x00000F00 0x00000FBF Trace METHOD Analyzer ETM Trace ON...

Page 30: ...PowerTrace Serial User s Guide 30 1989 2018 Lauterbach GmbH FAQ No information available ...

Page 31: ...e off or on RECORD The trace tool is armed and ready to receive data from target trace port It can be off or on RUNNING There are trace data coming in The trace tool is receiving and the trace buffer gets filled It can blink or be on or off Code Note Comment 1111111111111111 permanent on power good 0000000000000000 permanent off power off 1010100000000000 3x blinking power connector used but under...

Page 32: ... Error messages are displayed In the upper left corner of the Trace List window In the message line In the Area view window Advanced trace analysis commands like Trace STATistic Func Trace STATistic TASK or PERF List display only accurate results if the trace recording works error free ...

Page 33: ...ays to search for errors within the trace all of them will force TRACE32 to upload the complete trace information to the host 1 The Trace Find dialog In the Trace List window click Find to open a dialog with special search options Select Expert and enter flowerror in the items field The item entry is not case sensitive Use the Find First and Find Next buttons to jump to the next flowerror within t...

Page 34: ... a window The command corresponds to Find All described above 3 The command Trace Chart sYmbol This command starts a statistical analysis An additional symbol ERROR is shown if errors were found The search could take a long time depending on the used memory size of the trace module and the type of host interface Check the status to estimate the time ...

Page 35: ... Wrong endianness configuration bit byte word long Skipping wrong amount of bytes CRC or not Please see Diagnosis Check List Flowerror The traced data is not consistent with the code in the target memories Possible reasons are Memory contents have changed e g self modifying code Wrong endianness configuration bit byte word long Skipping wrong amount of bytes at the end of each Aurora frame CRC or ...

Page 36: ...ut of the data flow information if a Fifo overflow is likely to happen if supported ETM DataSuppress Trace Test Failure Messages Trace TestFocus supports a built in trace test This command loads a short test program to the target memory RAM and traces its execution Afterwards the recorded program flow and data pattern will be checked for any errors Analyzer data capture o k will be shown if the te...

Page 37: ...arget board Often messages such as Trace test failed not enough samples in the trace or Trace test failed pin connection error might indicate the source of the error Also check the voltage level of the reference voltage It is used as a reference for trigger and Vendor I O signals It should correspond to the amplitude of your trigger signal ID Preprocessor 0x80 Integrated Serial Error message Possi...

Page 38: ...flections Are all supply voltage levels stable when the trace port is active Double check your targets supply voltage A debug port fail can also happen in case of trace decoder errors based on inconsistent or damaged trace data Clear the trace buffer and try to single step instructions Do you see them displayed in the trace list window correctly 5 Check Some CPU types do not have dedicated trace p...

Page 39: ...lue stable Black and white scaling C shows the real usable range white stable usable black unstable The window gives you an idea about the signal integrity of your lanes Each lane can be displayed separately by using the up down buttons Mostly if you only see a black or red screen maybe with stripes then the receiver did not lock Either there is no trace signal or the target lane speed is not as e...

Page 40: ...Lauterbach GmbH 8 Check Is your TRACE32 software up to date It should be newer than build number 81148 Check http www lauterbach com updates html or ask your local support team for an update or contact stp support lauterbach com VERSION SOFTWARE ...

Page 41: ...EPORT MsgBItEndian TRACEPORT MsgBYteEndian TRACEPORT MsgWOrdEndian TRACEPORT MsgLOngEndian The following table shows the influence of each swap to the bit order No Swap 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 Bit Endianness 56 63 48 55 40 47 32 39 24 31 16 23 8 15 0 7 Byte Endianness 55 48 63 56 39 32 47 40 23 16 31 24 7 0 15 8 Word Endianness 63 48 47 32 31 16 15 0 Long Endianness 31 0 63 32...

Page 42: ...grity Cut out the GND plane below pads of connectors and components to reduce parasitic capacitance Avoid stubs e g by using only top or bottom layers Use back drilled vias if middle layers are used Ideally lanes should have a 100 impedance but 5 tolerance is suitable Use impedance controlled PCBs FR4 material is suitable for short distances 10cm 4inches Prevent use of signal vias Ideally stay on ...

Page 43: ...1 6 LA 1235 40pin Flex Cable Product number Product code Includes LA 3521 ACC PTSERIAL ETM 1 6 LA 1235 40pin flex cable LA 2770 Mipi34 ARM20 adapter LA 2114 34pin Half size Cable LA 3522 ACC PTSERIAL ETM 7 8 LA 1239 80pin flex cable Manufacturer Samtec Type 30 AWG Twinax Impedance 100 Capacitance 48 9 pF m Inductance 0 518 uH m Propagation Delay 4 79 ns m Shield Braid Silver Plated Copper Dielectr...

Page 44: ...r 34pin Samtec FTSH 117 01 L DV EJ SLA Connector 20pin Standard 2 54mm pin header with shroud PCB FR4 Manufacturer Yamaichi Type Flat ribbon cable Impedance 75 Capacitance 22 5pF ft Inductance 0 317µH ft Propagation Delay 1 7 ns ft Conductor 30 AWG Insulation Material PVC Contact Current Rating 0 5A Contact Resistance 30 m Length 45mm Pitch 1 27mm x 1 27mm ...

Page 45: ...GmbH LA 3522 ACC PTSERIAL ETM 7 8 LA 1239 80pin Flex Cable Manufacturer Samtec Type 30 AWG Twinax Impedance 100 Capacitance 48 9 pF m Inductance 0 518 uH m Propagation Delay 4 79 ns m Shield Braid Silver Plated Copper Dielectric FEP Jacket PVC Length 53 cm ...

Page 46: ... Synchronous reference clock bit clock CML output fraction of lane speed 1 1 1 2 1 20 1 25 1 30 1 34 1 40 1 50 max 6 25GHz VCCSENSE 1 2 3 3V TRIGIN 1 2 3 3V TRIGOUT 1 2 3 3V Asynchronous reference clock oscillator clock output HCSL 10MHz 500MHz or input LVDS LVPECL HCSL 100MHz 500MHz Synchronous reference clock bit clock CML output fraction of lane speed 1 1 1 2 1 20 1 25 1 30 1 34 1 40 1 50 max 6...

Page 47: ... 1989 2018 Lauterbach GmbH Timing Characteristics Maximum Lane Skew Additional Data PCB Device Connector Lane skew 10UI Impedance 100 differential Er 4 7 Material FR4 Samtec 40 pin ERF8 020 01 L D RA L TR 80 pin ERF8 040 01 L D RA L TR ...

Page 48: ... Port 0 follow the ARM HSSTP standard The debug signals will be routed to the 34pin debug connector on the top of the PowerTrace Serial module and can be accessed for debug cable The Serial Port 0 will also be used for non HSSTP targets In this case additional adapters could be necessary SerialPort 1 The Serial Port 1 is designed to support multiple interfaces The function of the signals change de...

Page 49: ...s The debug signals are not used by the PowerTrace Serial but they can be accessed via the MIPI conform 34pin connector on the top of the module The pinout of the SerialPort0 connector does not match the target trace connector pinout The necessary flex extension cable will change the signal order to match the HSSTP standard The correct target connector pinout for ARM HSSTP can be found here http w...

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