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Lauterbach MicroBlaze, Manual

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MicroBlaze Debugger and Trace     |    22

©

1989-2021

   Lauterbach     GmbH        

 

                   

                            

Memory Classes

The following memory classes are available:

Register Names

In TRACE32, the general purpose registers (

R0-R31

) and special purpose registers (e.g. 

MSR

 - machine 

state register, 

SLR

 - Stack low register etc.) are named according to the convention in the 

MicroBlaze 

Processor Reference Guide 

and shown accordingly in the 

Register.view

 window.

These names are also used in the disassembly views and the 

Data.Assemble

 command. This is in 

deviation from the Xilinx suggestions to use 

rmsr

, 

rslr

,  etc. in the context of assembly language.

Memory Class

Description

P

Program  memory

D

Data memory

Data.Assemble 0x1000 mfs r0, MSR

Data.Assemble 0x1004 mts SLR, r3

Summary of Contents for MicroBlaze

Page 1: ...MANUAL Release 09 2021 MicroBlaze Debugger and Trace ...

Page 2: ... 12 SYStem Up Errors 12 FAQ 12 Displaying MicroBlaze Core Configuration 13 CPU specific Implementations 14 Memory Accesses Causing Bus Errors 14 Breakpoints 15 Software Breakpoints 15 On chip Breakpoints 15 Breakpoints in ROM 15 Example for Breakpoints 16 SYStem Option BrkHandler Control writing of software break handler 17 SYStem Option BrkVector Configures an alternative breakvector 17 SYStem Op...

Page 3: ...m CONFIG MDM DebugPort Set core to debug 32 SYStem CONFIG MDM RESet Reset MDM configuration 32 SYStem CONFIG MDM view Display MDM configuration 33 SYStem CONFIG MDM UserInst Set default user BSCAN port 33 TrOnchip Commands 34 TrOnchip state Display on chip trigger window 34 TrOnchip RESet Set on chip trigger to default state 34 TrOnchip CONVert Adjust range breakpoint in on chip resource 34 TrOnch...

Page 4: ...es for different configurations of the debugger T32Start is only available for Windows General Commands general_ref_ x pdf Alphabetic list of debug commands Architecture specific information Processor Architecture Manuals These manuals describe commands that are specific for the processor architecture supported by your debug cable To access the manual for your processor architecture proceed as fol...

Page 5: ...uterbach TRACE32 infrastructure for software debugging over a single shared connection to the target board via Lauterbach hardware For more details see Integration for Xilinx Vivado int_vivado pdf NOTE As onchip breakpoints require additional FPGA resources and may slow down the maximum frequency of a MicroBlaze design it is necessary to explicitly configure them in the FPGA design Trace via the M...

Page 6: ... Cable from the target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 Connect the Debug Cable to the target 6 Switch the target power ON 7 Configure your debugger e g via a start up script Power down 1 Switch off the target power 2 Disconnect the Debug Cabl...

Page 7: ...dware memecfx12lc stopandgo download bit The FPGA configuration can be done using Xilinx Vivado or its predecessor Xilinx iMPACT or the TRACE32 command JTAG PROGRAM or the old version of the command JTAG LOADBIT After starting the TRACE32 software enter the following commands for connecting to the target and load a sample file Multicore configuration will be required in most cases even when there ...

Page 8: ...icroBlaze processors select which one you want to debug 4 Attach to the target and enter debug mode using the multicore settings from above This command resets the CPU and enters debug mode After executing this command memory and registers can be accessed SYStem Option LittleEnd ON SYStem CONFIG IRPOST 28 SYStem CONFIG IRPRE 8 SYStem CONFIG DRPOST 2 SYStem CONFIG DRPRE 1 Note the indicating decima...

Page 9: ...ith cygdrive c By using the option CYGDRIVE TRACE32 internally converts this prefix to the correct syntax e g to c on windows hosts Refer for more information to Data LOAD Elf 6 Open the disassembly and register windows 7 You are now ready to debug your program CD demo microblaze hardware ml403 mb v710d xmtc 100b noddrram Data LOAD Elf sieve_00000000 elf CYGDRIVE Data List Open disassembly window ...

Page 10: ...ively use the following command in the TCL console assuming your MDM has the default instance name mdm_0 4 Connect an appropriate clock signal to the TRACE TRACE_CLOCK port and export the TRACE TRACE_DATA signal Also export the that feeds TRACE TRACE_CLOCK Leave TRACE TRACE_CLK_OUT and TRACE TRACE_CTL unconnected 5 Use ODDR buffers to create DDR double data rate signalling on the external trace po...

Page 11: ...s need to contain debug information It is recommended to compile MicroBlaze software with the GCC option g3 The option g creates debug info that does not work well with TRACE32 Also keep in mind that using code optimization can cause problems with debugging NOTE It is recommended to compile MicroBlaze software with the GCC option g3 ...

Page 12: ...volves rapidly and therefore regular updates of the debugger software are necessary Note that the software downloads on the LAUTERBACH website represent stable releases but are not necessarily the latest versions If the problems persist after updating from the website please contact LAUTERBACH support All The target FPGA is not configured correctly The FPGA configuration e g via ACE files can be d...

Page 13: ...aze Core Configuration As the Microblaze core is configurable the available debug features depend on the current core The configuration of the core can be displayed using the command per When pointing the mouse at an entry the debugger displays an explanation in the status line ...

Page 14: ...tinuation of the program Therefore inside an exception handler MSR EIP 1 the debugger uses a different memory access method that preserves the correct system state but does not detect bus errors In this case the contents of invalid memory regions will show random data Under Linux the most common case for this problem is when a system call branches to the hardware exception vector on 0x20 In this c...

Page 15: ...y are also referred to as hardware breakpoints in non Lauterbach terminology The following list gives an overview of the usage of the on chip breakpoints by TRACE32 ICD Instruction breakpoints stop the core when it reaches a certain program location Read Write address breakpoints can stop the core upon read or write data accesses Data breakpoints stop the program when a specific data value is writ...

Page 16: ... TRACE32 correctly for this configuration is The following breakpoint combinations are possible Software breakpoints On chip breakpoints Map BOnchip 0x0 0x0FFFFF Break Set 0x100000 Program Software Breakpoint 1 Break Set 0x101000 Program Software Breakpoint 2 Break Set 0xx Program Software Breakpoint 3 Break Set 0x100 Program On chip Breakpoint 1 Break Set 0x0ff00 Program On chip Breakpoint 2 ...

Page 17: ...ctor table pre loaded with the memory image must contain a breakpoint handler If all program memory is read only consider the use of OnChip breaks as alternative SYStem Option BrkVector Configures an alternative breakvector Use this option to set an alternative address for the software breakpoint handler created by the debugger Changing the default address is necessary when the vector 0x18 is occu...

Page 18: ... HLL single steps Useful to prevent interrupt disturbance during HLL single stepping SYStem Option LittleEndian Select little endian mode Selects endianness SYStem Option MMUSPACES Separate address spaces by space IDs Default OFF Enables the use of space IDs for logical addresses to support multiple address spaces NOTE For additional information see SYStem Option BrkHandler Format SYStem Option IM...

Page 19: ...e register R1 R31 caches and UTLB NOTE SYStem Option MMUSPACES should not be set to ON if only one translation table is used on the target If a debug session requires space IDs you must observe the following sequence of steps 1 Activate SYStem Option MMUSPACES 2 Load the symbols with Data LOAD Otherwise the internal symbol database of TRACE32 may become inconsistent Dump logical address 0xC00208A ...

Page 20: ...les STDIO via MDM UART Sample script for opening term window attached to MDM UART core Format SYStem Option DUALPORT ON OFF Format SYStem Option MDMSINGLELMB ON OFF OFF Use a separate LMB master for each core This is the default setting In this mode the debugger will always use the LMB master corresponding to the core If the core at debug port x is debugged the debugger uses LMB master x Use this ...

Page 21: ...croBlaze Debugger and Trace 21 1989 2021Lauterbach GmbH To confirm if the MDM UART is enabled in your design open the peripheral window via the PER command and look for the section MDM UART Configuration ...

Page 22: ...w register etc are named according to the convention in the MicroBlaze Processor Reference Guide and shown accordingly in the Register view window These names are also used in the disassembly views and the Data Assemble command This is in deviation from the Xilinx suggestions to use rmsr rslr etc in the context of assembly language Memory Class Description P Program memory D Data memory Data Assem...

Page 23: ... of multiple cores in an FPGA design Instead of using the deprecated options the following sequence is recommended to attach to a specific core in an FPGA design Note that all the cores inside an FPGA share identical multicore settings PRE POST values because they are accessed via the same TAP controller implemented in the Xilinx MDM IP block Format SYStem CPU cpu cpu MicroBlaze ZYNQ ULTRASCALE PM...

Page 24: ... and tristate the debug port Default OFF If the system is locked no access to the debug port will be performed by the debugger While locked the debug connector of the debugger is tristated The main intention of the SYStem LOCK command is to give debug access to another tool Format SYStem JtagClock rate SYStem BdmClock rate deprecated fixed 1 000 000 25 000 000 NOTE Buffers additional loads or high...

Page 25: ...Format SYStem MemAccess mode mode Denied Enable StopAndGo Denied No memory access is possible while the CPU is executing the program Enable CPU depre cated Accesses are performed via the MicroBlaze Debug Module StopAndGo Temporarily halts the core s to perform the memory access Each stop takes some time depending on the speed of the JTAG port the number of the assigned cores and the operations tha...

Page 26: ... of NoDebug Go Resets the target with debug mode enabled and prepares the CPU for debug mode entry After this command the CPU is in the system up mode and running Now the processor can be stopped with the break command or until any break condition occurs Up Resets the target and sets the CPU to debug mode After execution of this command the CPU is stopped and prepared for debugging All register ar...

Page 27: ...o tristate mode Please note nTRST must have a pull up resistor on the target TCK can have a pull up or pull down resistor other trigger inputs need to be kept in inactive state Format SYStem CONFIG parameter number_or_address SYStem MultiCore parameter number_or_address deprecated parameter CORE core parameter JTAG DRPRE bits DRPOST bits IRPRE bits IRPOST bits TAPState state TCKLevel level TriStat...

Page 28: ... This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest TAPState default 7 Select DR Scan This is the state of the TAP controller when the debugger switches to tristate mode All states of the JTAG TAP controller are selectable TCKLevel default 0 Level of TCK signal when all debuggers are tristated TriState default OFF If seve...

Page 29: ...Instruction register length of Core A 3 bit Core B 5 bit Core D 6 bit SYStem CONFIG IRPRE 6 IR Core D SYStem CONFIG IRPOST 8 IR Core A B SYStem CONFIG DRPRE 1 DR Core D SYStem CONFIG DRPOST 2 DR Core A B SYStem CONFIG CORE 0 1 Target Core C is Core 0 in Chip 1 Core A Core B Core C Core D TDO TDI Chip 0 Chip 1 ...

Page 30: ...021Lauterbach GmbH TapStates 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15 Test Logic Reset ...

Page 31: ...fore you have to assign the core_index and the chip_index for every core Usually the debugger does not need further information to access cores in non generic chips once the setup is correct Generic Chips Generic chips can accommodate an arbitrary amount of sub cores The debugger still needs information how to connect to the individual cores e g by setting the JTAG chain coordinates Start up Proce...

Page 32: ...odule MDM is to be debugged by the current GUI The first core connected to the MDM is always numbered 0 Connecting to the core will fail if the selected number exceeds the number of debug ports of the MDM If the command is not used or if the special value NONE is used the core index is determined by the CORE ASSIGN and SYStem CONFIG CORE commands This method is deprecated do not use it in new scri...

Page 33: ...fails the debugger will try the other instructions Therefore it is only required that you set the correct instruction if you either have multiple MDM instances in your FPGA design and wish to select a specific one or have other IP in your FPGA design e g an Integrated Logic Analyzer ILA that uses a JTAG user instructions and want to avoid disturbing that IP with the debugger s attempt to connect t...

Page 34: ...t be programmed into the breakpoint it will automatically be converted into a single address breakpoint when this option is active This is the default Otherwise an error message is generated Format TrOnchip state Format TrOnchip RESet Format TrOnchip CONVert ON OFF deprecated Use Break CONFIG InexactAddress instead TrOnchip CONVert ON Break Set 0x1000 0x17ff Write Break Set 0x1001 0x17ff Write TrO...

Page 35: ... or breakpoint to a complex variable the on chip break resources of the CPU may be not powerful enough to cover the whole structure If the option TrOnchip VarCONVert is set to ON the breakpoint will automatically be converted into a single address breakpoint This is the default setting Otherwise an error message is generated Format TrOnchip VarCONVert ON OFF deprecated Use Break CONFIG VarConvert ...

Page 36: ... TaskPageTable task_magic task_id task_name space_id 0x0 cpu_specific_tables root The root argument can be used to specify a page table base address deviating from the default page table base address This allows to display a page table located anywhere in memory range address Limit the address range displayed to either an address range or to addresses larger or equal to address For most table type...

Page 37: ...f the given process Specify one of the TaskPageTable arguments to choose the process you want In MMU based operating systems each process uses its own MMU translation table This command reads the table of the specified process and displays its table entries For information about the first three parameters see What to know about the Task Parameters general_ref_t pdf See also the appropriate OS Awar...

Page 38: ... command reads the MMU translation table of the kernel and lists its address translation TaskPageTable task_magic task_id task_name space_id 0x0 Lists the MMU translation of the given process Specify one of the TaskPageTable arguments to choose the process you want In MMU based operating systems each process uses its own MMU translation table This command reads the table of the specified process a...

Page 39: ...ation into the debugger internal static translation table if range or address have a space ID loads the translation table of the specified process else this command loads the table the CPU currently uses for MMU translation KernelPageTable Loads the MMU translation table of the kernel If specified with the MMU FORMAT command this command reads the table of the kernel and copies its address transla...

Page 40: ... software breakpoints Default OFF Enable this system option in order to optimize tracing of software breakpoints When hitting a software break earlier versions of MicroBlaze jump to a software break handler and loop there until the debugger detects the break As this can last some milliseconds the trace buffer will contain irrelevant trace data By enabling the option is enabled the debugger sets an...

Page 41: ...entical with those used for debugging a MicroBlaze core Also ensure that the debugger is in SYStem down mode before configuring your FPGA Configuring the FPGA will break the communication link between the debugger and the MicroBlaze core if your debugger is in SYStem up mode Configuration using compressed bitstreams is supported It is recommended to configure the target with the configuration opti...

Page 42: ...hat converts the PPC400 pinout to that of the 14 pin Xilinx JTAG connector which is listed below Signal Pin Pin Signal TDO 1 2 N C TDI 3 4 TRST N C 5 6 VCCS TCK 7 8 N C TMS 9 10 N C HALT 11 12 N C N C 13 14 KEY N C 15 16 GND Pinout of PPC400 debug cable Signal Pin Pin Signal GND 1 2 VREF GND 3 4 TMS GND 5 6 TCK GND 7 8 TDO GND 9 10 TDI GND 11 12 NC GND 13 14 NC Pinout of Xilinx JTAG connector NOTE...

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