Lauterbach M32R Manual Download

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M32R Debugger and Trace | 30

1989-2023

Lauterbach

Memory Classes

Memory Class

Description

D,C

Data memory. Memory seen from the cores point of view.

Program memory.

Summary of Contents for M32R

Page 1: ...MANUAL Release 02 2023 M32R Debugger and Trace...

Page 2: ...em JtagClock Define JTAG clock 13 SYStem LOCK Lock and tristate the debug port 13 SYStem MemAccess Select memory access mode 14 SYStem Mode Establish the communication with the target 15 SYStem Option...

Page 3: ...Opens configuration panel 22 Security Levels of the M32R Family 23 Security Level 23 Flash Erase if Device is secured 24 General Restrictions and Hints 25 Floating Point Formats 26 Integer Access Keyw...

Page 4: ...M32R Debugger and Trace 4 1989 2023 Lauterbach M32R Debugger and Trace Version 10 Feb 2023...

Page 5: ...of Documents for New Users Architecture independent information Training Basic Debugging training_debugger pdf Get familiar with the basic features of a TRACE32 debugger T32Start app_t32start pdf T32S...

Page 6: ...TRACE32 PowerView Type at the command line WELCOME SCRIPTS or choose File menu Search for Script You can now search the demo folder and its subdirectories for PRACTICE start up scripts cmm and other d...

Page 7: ...m the target while the target power is off 2 Connect the host system the TRACE32 hardware and the Debug Cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware...

Page 8: ...ace Normally the default value is 10 0 MHz but the it can be increased up to 25 MHz 4 Inform the debugger about read only and none readable address ranges ROM FLASH The BreakOnchip information is nece...

Page 9: ...have to be set e g chip select register 7 Load the program The format of the Data LOAD command depends on the file format generated by the compiler It is recommended to use the option Verify that ver...

Page 10: ...WinPOS command B Select the ICD device prompt WinClear Clear all windows SYS CPU M32196 Select CPU SYS JC 15000000 Choose JTAG frequency SYStem Up Reset the target and enter debug mode MAP DENYACCESS...

Page 11: ...ller is allowed There is logic added to the JTAG state machine By default the debugger supports only one processor in one JTAG chain If the processor is only one member of a JTAG chain the debugger ha...

Page 12: ...ONFIG Configure debugger according to target topology The SYSTem CONFIG command group is not supported for the M32R SYStem CPU Select target CPU Selects the processor type The processor type must be s...

Page 13: ...ectly e g memory is flickering decrease the JtagClock SYStem LOCK Lock and tristate the debug port Default OFF If the system is locked no access to the debug port will be performed by the debugger Whi...

Page 14: ...le CPU deprecated Provides access to memory while the core is running StopAndGo Temporarily halts the core s to perform the memory access Each stop takes some time depending on the speed of the JTAG p...

Page 15: ...capability Format SYStem Mode mode SYStem Down alias for SYStem Mode Down SYStem Up alias for SYStem Mode Up mode Down Up Down Disables the debugger default The state of the CPU remains unchanged The...

Page 16: ...ons After single step the interrupt mask bits are restored to the value before the step SYStem Option IMASKHLL Disable interrupts while HLL single stepping Default OFF If enabled the interrupt mask bi...

Page 17: ...cess to the device By default use If the device is blank the debugger automatically uses 12 time 0xFF per default Then no SYS OPTION KEYCODE command is needed The number and location of bytes depends...

Page 18: ...e Allow debugger to drive JTAG and reset Default OFF If this option is OFF the JTAG signals and nRST line are never driven by the debugger SYStem state Display SYStem state window Displays the SYStem...

Page 19: ...has trace support When the option is set to READ WRITE READWRITE the CPU generates data trace messages according to the selected access type SYStem Option STALL Trace message overrun control Default O...

Page 20: ...d on the processor frequency High frequencies can cause electrical connection problems during the record of trace messages SYStem Option TRDATA Trace port width Default 8 The option can be set when th...

Page 21: ...rmal if necessary The OCE can perform more operations than TRACE32 offers with it s user interface e g build a chain of breakpoints The on chip trigger unit events can be also used to control the trac...

Page 22: ...and Trace 22 1989 2023 Lauterbach TrOnchip state Opens configuration panel Control panel to configure the on chip breakpoint and trace registers The details are described in section TrOnchip Format T...

Page 23: ...l even flashing is not possible The debugger generates an error message and remains in down state Security Level 1 The debugger reaches up state but all read write access to the Flash memory to RAM to...

Page 24: ...Enter the default Security Code and system up the debugger or just system up the debugger default Security Code is used implicitly Another way is to clear the flash memory of the CPU by using the inst...

Page 25: ...M is enabled the debugger won t update correctly the interrupt disable bit in the SR register in case the code executed the DI instruction Use SYStem Option IPLDI to switch the behavior Ignore RESET M...

Page 26: ...6 bit F32 Fractional fixed point 32 bit NOTE Fractional floating point numbers are always displays with a fixed precision i e a fixed number of digits Small fractional numbers can have many non releva...

Page 27: ...sense line only RST TDI TMS TCK In normal operation mode the driver is enabled but it can be disabled to give another tool access to the JTAG port In environments where multiple tools can access the J...

Page 28: ...12 VSS TRDATA6 13 14 TRDATA7 VCC 15 16 EVENT0 EVENT1 17 18 EVENT2 EVENT3 19 20 N C Pins Connection Description Recommendations 1 TRCLK Trace Clock 2 VSS System Ground Plan Connect to digital ground 3...

Page 29: ...M32R Debugger and Trace 29 1989 2023 Lauterbach 15 VCC Target VCC Just used for voltage reference 16 EVENT0 Event output 17 EVENT1 Event output 18 EVENT2 Event output 19 EVENT3 Event output 20 N C...

Page 30: ...M32R Debugger and Trace 30 1989 2023 Lauterbach Memory Classes Memory Class Description D C Data memory Memory seen from the cores point of view P Program memory...

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