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Lauterbach ICE Emulator, Manual

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Lauterbach ICE Emulator Manual Download Page 33

  ICE Emulator for 8051

 

    33     

  

©1989-2019 Lauterbach GmbH

Bank drivers are special subroutines (max. length 256 bytes) to set the bank or an external MMU:

External

External banked systems use a register or output pins of the CPU to generate the upper memory 
addresses. These lines must be feedback to the emulator with the bank probe. Unused inputs of the bank 
probe must be grounded (or jumpered to ground pin). 

This example uses a common program area on 0--3fffh a banked area from 4000--7fff with 4 banks

This example selects the bank by 

internal

 port 3 bit 2 and 4:

org 5ffh

db   1

; select internal mode

bank:

org 600h

; destination area in system memory

push dpl

push dph

mov a,r6

mov dptr,4000h

lcall 700h

pop dph

pop dpl

ret

; physical bank

; set DPTR to banked area

; subroutine to write byte to target

; system setting the page register 

; in the EPROM

; return

map.res

map.mirror  p:0x0--0x3fff p:0x10000

map.mirror  p:0x0--0x3fff p:0x20000

map.mirror  p:0x0--0x3fff p:0x30000

system.bankfile banksel.bnk

system.up

; reset mapper

; mirror for common area

; load bank file

; bank switching program

input:

r0,r1

r6

r4

r5

; address

; bank

; read/write

; program/data

usable:

r7,a,b,psw

Summary of Contents for ICE Emulator

Page 1: ...A PLCC 13 80C152JB PLCC 13 C515C 13 C505C 14 Basics 15 Emulation Modes 15 SYStem Clock Clock generation 16 SYStem CPU CPU modes 17 SYStem Access Dualport access 17 General SYStem Settings and Restrictions 18 General Restrictions 18 Special I O Register Module M582 18 Special I O Register Module MCL580 21 Special I O register Module 517E 22 Internal Memory 23 SYStem Line Bus configuration 24 SYStem...

Page 2: ... State Analyzer 38 Keywords for the Trigger Unit 38 General 8051 Keywords for the Trigger Unit 38 80152 Keywords for the Trigger Unit 39 Keywords for the Display 40 Dequeueing 40 Port Analyzer 41 Keywords for the Port Analyzer 41 Additional Trace Channels 42 Module 8051 42 Module M582 42 Adapter M582 C562 42 Adapter M582 C552 42 Module M592 43 Module S517 C535 43 Module 80152 43 Module MCL580 44 S...

Page 3: ...en target Power down Switch off target first then emulator P 000072 KEILS KEILS sieve 6F MIX AI E w d l addr line code label mnemonic comment P 00006E 351D addc a 1D a primz P 000070 F51F mov 1F a k a 32 while k SIZE P 000072 C3 clr c P 000073 E520 mov a 20 P 000075 9413 subb a 13 P 000077 E51F mov a 1F a k P 000079 9400 subb a 0 P 00007B 30D202 jnb ov 80 P 00007E B2E7 cpl acc 7 E w v f l c E w r ...

Page 4: ...e target hardware easier It describes a typical setup with frequently used settings It is recommended to use the programming language PRACTICE to create a batch file which includes all necessary setup commands PRACTICE files cmm can be created with the PRACTICE editor pedit Command PEDIT file name or with any other text editor A basic setup file includes the following parts 1 Set cpu type and mode...

Page 5: ...ory access of the CPU This means the use of internal or external memory the protection of a memory bank etc Address ranges must be defined by using memory classes 5 Select frequency optional The CPU can be clocked by an internal emulator or external target clock source If the internal clock is used the clock is provides by the VCO of the emulator The setting of the internal clock is done by the vc...

Page 6: ...or information about the load command for your compiler see Compiler 8 Set breakpoints optional There are several ways to set breakpoints Command Break Set Breakpoints can be displayed using the Break List command 9 Start application Application can be started with giving a break address For example go main starts the application and stops at symbol main 10 Stop application optional Application ca...

Page 7: ...ICE Emulator for 8051 7 1989 2019 Lauterbach GmbH Troubleshooting No Information available ...

Page 8: ... error without exe cuting SCREEN OFF some windows will not be updated SYStem POLLING SLOW will set a lower frequency for target state checks e g power reset jtag state It will take longer for the debugger to recognize that the core stopped on a breakpoint SETUP URATE 1 s will set the default update frequency of Data List Data dump Variable windows to 1 second the slowest possible setting Prevent u...

Page 9: ...ipt with the DO command from system settings cmm in your TRACE32 system directory create system settings cmm if it does not exist https www lauterbach com faq targetc cmm Wrong Location after Break Ref 0030 Why is the location after break wrong Most emulators use some bytes of user stack for the break system Therefore it is necessary to have valid stack if single step or breakpoints are used Bank ...

Page 10: ...sources can be stopped while the user program has been stopped Additional registers contain information about pending interrupts etc Some bond out chips are Combi CPUs which can emulate more than a derivative of the 8051 family A non bond out emulator uses the original chip which is readily available their local distributor There are no additional lines and information available about the internal...

Page 11: ...TASK or on the appropriate pages in the user guide This procedure can also be used to keep the emulator active for any interrupt requests after an user programm break 8051 Trace Internal Registers Ref 0009 How do I trace a chip internal data transfer from one register to an other Neither a bond out based nor a non bond out emulator has access to the internal busses between the registers Also it is...

Page 12: ...1 ROM version no external memory without bondout chip a piggy back version of the 8051 chip is used on the 8051 adapter The OKI 85C154VS and the MHS 80C31P8 P16 are such piggy back versions of 8051 They require an additional small adapter cable between the EPROM socket and the 26 pin connector on the module C A B Con A Con B Jumper C no Piggy Back not used not used closed OKI 85C154VS connected op...

Page 13: ... system window Set bridge array in position A for 83C152JA emulation or position B for romless version and for DMA 80C152JB PLCC Mount adapter 80152JB PLCC and select CPU type 80C152JB in system window Depending on the used bus mode set the bridge array as shown in position A or B C515C For proper operation all switches of DIPSWITCH S101 must be closed and all switch of DIPSWITCH S100 must be open...

Page 14: ...he equivalent pin of S100 must be open For digital functions the appropriate pin of S101 must be open and the equivalent pin of S100 must be closed Never close or open equivalent pins of S101 and S100 simultaneously For emulation the A D unit of the C515C must be supplied S100 pin 1 C505C Port10 pin 2 C505C Port11 pin 3 C505C Port12 pin 4 C505C Port13 pin 5 C505C Port14 pin 6 C505C Port15 pin 7 C5...

Page 15: ...wn RESet VCO 1 000ms OFF I8051 Up Analyzer Low TimeOut Running I8051GB Monitor Mid 50 000us ON I80152JA RESet ResetDown High ALways I80152JB ResetUp Line EA O80154 cpu type NoProbe Access OFF Line EOW S80515A I8051 AloneInt Slow ON OFF S80517A AloneExt Fast ALways Running S80535 EmulInt Advanced ON S80537 BankMode EmulExt Denied Option ALways V80552 OFF DUMMY V80562 INTern BankFile IOSTOP Line EBE...

Page 16: ...e in tristate mode Reset Up Target has power drivers are logically in inactive state but not tristate Alone Internal Probe is running with internal clock driver inactive This mode is used for standalone operation Alone External Probe is running with external clock driver inactive Emulation Internal Probe is running with internal clock strobes to target are generated Emulation External Probe is run...

Page 17: ...m is down If DUMMY Cycle is active and the access mode FAST or ADVANCED is selected sometimes wrong data values can appear in the trace of DUMMY cycles Format SYStem CPU type mode I8031 V80851 Format SYStem Access Slow Fast Advanced Denied Slow Dualport access while ALE is active for slow clock Fast Dualport access while DUMMY Cycle for medium clock Advanced Forced Dualport access while DUMMY Cycl...

Page 18: ...rnal program memory area of a microcontroller EA 1 should always mapped internal because it s not possible to load a program into this area Power Down Mode On boards till rev 5 there is no support for power down mode because the CPU oscillator stops immediately and therefore several errors can appear Newer boards support power down modes while the emulation is running The dualport access mode must...

Page 19: ...special function registers of the 80C517 are also available when emulating the 80C515 For correct emulation of the 80C515 80C535 don t use the following SFR s 0ECH 0EDH 0EEH 0EFH 0F6H 0F7H 0FAH XRAM Access only 515A 517A When the XRAM is enabled the XMAP1 SFR must be set otherwise the breakpoints and analyzer trace will not work in this address range DMA cycles The trigger unit can t distinguish b...

Page 20: ...ow Depending on the selected CPU some of the interrupt sources may be inhibited Within the 83C581 mode check flags RI TI and IFE to decide weather a SIO 0 or E2PROM interrupt has occurred 7 6 5 4 3 2 1 0 Level 1 Code Level 0 Code Internal Source Level Code 51 851 662 652 562 552 external 0 0 0 0 0 x x x x x x timer 0 0 0 0 1 x x x x x x external 1 0 0 1 0 x x x x x x timer 1 0 0 1 1 x x x x x x SI...

Page 21: ...unning A RESET sets the ISR to 0FFH When an interrupt occurs the corresponding level code appears as defined below Depending on the selected CPU some of the interrupt sources may be inhibited 7 6 5 4 3 2 1 0 Level 1 Code Level 0 Code Internal Source Level Code external 0 0 0 0 0 timer 0 0 0 0 1 external 1 0 0 1 0 timer 1 0 0 1 1 SIO 0 0 1 0 0 I2C 0 1 0 1 Derivative Int1 0 1 1 0 Derivative Int2 0 1...

Page 22: ...eadable and invisible while user program is running A RESET set the IS0 1 to 0FFH When an interrupt of level 0 1 2 or level 3 occurs the corresponding level code appears as defined below IS0 IS1 7 6 5 4 3 2 1 0 IS0 Level 1 Level 0 IS1 Level 2 Level 3 Internal Source Level Code external 0 0 0 0 0 timer 0 0 0 0 1 external 1 0 0 1 0 timer 1 0 0 1 1 SIO 0 0 1 0 0 timer 2 0 1 0 1 SIO 1 0 1 1 0 comp tim...

Page 23: ...the breakpoint location will not trigger the breakpoint The breakpoint list commands list only one memory class b s d 0x40 w set direct addressed breakpoint mov a 0x40 the breakpoint is triggered mov r0 40 mov a r0 the breakpoint is not triggered b s b 0x0 r set bit addressed breakpoint movb 0x0 c the breakpoint is triggered mov r0 20 mov r0 a the breakpoint is not triggered b l list program break...

Page 24: ...ys ON OFF EBEN ALways ON OFF EA ALways EA line is always active This option must be chosen if a chip without bond out capabilities is emulated e g 8031 EA ON EA line is connected to the target system EA OFF EA line is always off EBEN ALways EBEN line is always active The opfetch is made via P5 P6 EBEN ON EBEN line is connected to the target system EA OFF EBEN line is always off LINE EA LINE EBEN O...

Page 25: ...store address seems to be the next opfetch behind the data access but that is true because the CPU makes a dummy cycle before the data access with the address of the next opcode or the prestore address is the address of a dualport access while access mode Fast or Advanced Switch DUMMY off decreases the really number of cycles counting in the counter window Format SYStem Line option option EW OFF R...

Page 26: ...top all interrupts are inhibit UART stops after sending or receiving actual data and inhibits capture registers and the TR2 input IOSTOP has no effect on the AD converter the PWM circuitry the I2C logic and the EEPROM When IOSTOP is switched off all internal IO devices keep running while emulation stops If IOSTOP is active and EA 1 and the program memory is mapped external a Data window shows not ...

Page 27: ...0C152JB PLCC DMA P5 FETCH P5 80C152JD PLCC SFR DMA P5 FETCH P5 SFR Use only the SFR of the current emulated CPU All other SFR s of the emulation CPU 80C152J are available but not relevant for a correct emulation DMA C In the microcontroller mode the fetch of the program is performed via the port P5 P6 of the 80C152JB In this bus mode the emulator can t support DMA Cycles DMA P5 If the alternative ...

Page 28: ...ck error check Format SYStem Option TestClock ON OFF ON The clock test circuit is active Clock fails will be detected by the emulator system The emulator changes to reset state OFF No clock check The external clock may be switched off but no trace of program and data is possible ...

Page 29: ...ble exception Format eXception Activate RES ON OFF Format eXception Activate OFF RES Activates the RES line OFF No activation of any exception line Format eXception Enable RES ON OFF Format eXception Enable OFF Format eXception Enable ON RES Enables the RES line ON Enables all exception line OFF Disables all exception lines ...

Page 30: ...r Pulse ON OFF Format eXception Trigger RES ON OFF Format eXception Trigger T0 ON OFF Format eXception Trigger T1 ON OFF Format eXception Trigger OFF Format eXception Trigger ON INT0 Trigger on INT0 line INT1 Trigger on INT1 line P Trigger on P line RES Trigger on RES line T0 Trigger on T0 line T1 Trigger on T1 line ON Trigger on all exception lines OFF No trigger on any exception lines ...

Page 31: ... eXception Pulse INT1 width period Format eXception Pulse RES width period Format eXception Pulse T0 width period Format eXception Pulse T1 width period Format eXception Pulse OFF INT0 Stimulate INT0 line INT1 Stimulate INT1 line RES Stimulate RES line T0 Stimulate T0 line T1 Stimulate T1 line OFF No stimulation on any exception line ...

Page 32: ... used to set microcontroller ports or external MMUs in the target system The bank file consists of a code number defining the bank operation mode and a code area which consists of a subroutine to set the correct bank state Writes to internal CPU ports may be executed directly while ports in target systems must be accessed by a special system call to address 700H and 715H Translation of logical ban...

Page 33: ...om 4000 7fff with 4 banks This example selects the bank by internal port 3 bit 2 and 4 org 5ffh db 1 select internal mode bank org 600h destination area in system memory push dpl push dph mov a r6 mov dptr 4000h lcall 700h pop dph pop dpl ret physical bank set DPTR to banked area subroutine to write byte to target system setting the page register in the EPROM return map res map mirror p 0x0 0x3fff...

Page 34: ...banked eprom external banking from pod org 5ffh db 2 using external banking logic org 600h banking mov a r6 mov c acc 0 mov p3 2 c mov c acc 1 mov p3 4 c ret bank to acc address bit 16 to port 3 bit 2 address bit 17 to port 3 bit 4 org 5ffh db 2 select external mode bank org 600h destination area in system memory push dpl push dph mov a r6 mov dptr 0a0h lcall 700h pop dph pop dpl ret physical bank...

Page 35: ...0 0x7fff p 0x50000 map mirror p 0x0 0x7fff p 0x20000 reset mapper mirror for common area map ram p 0 0ffff map ram p 78000 7ffff map ram p 48000 4ffff map ram p 58000 5ffff map ram p 28000 2ffff map intern map memory in physical banks symbol reset mmu reset mmu create p 00000 07fff p 00000 07fff mmu create p 08000 0ffff p 78000 7ffff mmu create p 00000 07fff p 70000 77fff mmu create p 18000 1ffff ...

Page 36: ...ICE Emulator for 8051 36 1989 2019 Lauterbach GmbH Memory Access Routines Addr Function Address Data Result 700H MemWrite DPTR A 715H MemRead DPTR A ...

Page 37: ... Access Class Description P Program X External Data XP External or Program D Internal direct access I Internal indirect access B Internal bit addressing EP Program emulation memory access EX External Data emulation memory access C CPU access E Emulation memory access ...

Page 38: ...RRDWRBIT or DIRRDWRBYTE X X X X DIRectWRite DIRWRBIT or DIRWRBYTE or DIRRDWRBIT or DIRRDWRBYTE X X X X DIRRDBIT Address constant for a internal bit read cycle read X X X X DIRRDBYTE Address constant for a internal direct read cycle read X X X X DIRRDWRBIT Address constant for a internal bit modify cycle read X X X X DIRRDWRBYTE Address constant for a internal byte modify cycle read X X X X DIRWRBI...

Page 39: ... X X INT0 P32 Interrupt 0 X X INT1 P33 Interrupt 1 X X MULDIVCYC Multiply or division cycle X X X X OPFetch Program memory read cycle X X X X PORT Signal from port analyzer X X Program FETCH or DUMMY or READCODE or MULDIVCYC X X X X P30 P37 Port 3x X X Read DIRectReaD or EXTREAD X X X X READCODE CDATA MOVC cycle X X X X RXD P30 ReceiverData cycle X X X TIMER T0 or T1 X X Timer0 P34 X X Timer1 P35 ...

Page 40: ... the opfetch If an interrupt acknowledge cycle was sampled by the analyzer the last opfetch before the cycle intack was not executed If DUMMY is off two intack cycles appear otherwise three cycles are shown in the analyzer list window While multiplication and division a pseudo cycle MULDIV appears in the analyzer list window P10 P17 Port 1 B0 B7 Bank probe inputs ...

Page 41: ...cted to ports 0 1 2 3 4 5 6 and 7 port 8 cannot be traced On 80152 probes the port analyzer is always connected with P5 P6 of the target Keywords for the Port Analyzer 00 07 Port 0 10 17 Port 1 20 27 Port 2 30 37 Port 3 40 47 Port 4 50 57 Port 5 X0 X7 Port 6 or free channels Y0 Y7 Port 7 or free channels ...

Page 42: ... P40 P47 P50 P57 Front view ___ o o o o X o o o o o o o o PXx o o o o X o o o o o o o o PYx G G G G 7 6 5 4 3 2 1 0 G GND X NC PX0 PX7 PY0 PY7 Front view ___ o o o o X o o o o o o o o P4x o o o o X o o o o o o o o P5x G G G G 7 6 5 4 3 2 1 0 G GND X NC P40 P47 P50 P57 Front view 7 6 5 4 3 2 1 0 S D ___ o o o o X o o o o o o o o P5x o o o o o o o o o o o o o V G G G G G G G G G G V V G GND V 5V P50...

Page 43: ...kwards R N G G ___ o o o o X o o o o o o o o PXx o o o o X o o o o o o o o PYx G V G G G 7 6 5 4 3 2 1 0 G GND X NC PX0 PX7 PY0 PY7 V 5V R VAREF N VAGND For use without target the AVREF have 10 k in series Pin 4 VPD of the socket of the 80C515 535 is not connected Pin 37 VBB of the socket of the 80C515 535 is not connected G G G 7 6 5 4 3 2 1 0 ___ V x o o o o o o o o o o o P7x o o o o o o o o o o...

Page 44: ...ICE Emulator for 8051 44 1989 2019 Lauterbach GmbH Module MCL580 Front view ___ o o o o o o o o o o o o o PXx o o o o o o o o o o o o o PYx G G G G G 7 6 5 4 3 2 1 0 G GND PX0 PX7 PY0 PY7 ...

Page 45: ...FF PASCAL SYSTEM51 PASCAL KSC Software Systems OMF 51 No type information PLM PL M 51 Intel Corporation OMF 51 PLM PLM51 TASKING IEEE OMF also possible CPU Tool Company Host WINDOWS CE PLATF BUILDER Windows CODE BLOCKS C TEST Windows ADENEO X TOOLS X32 blue river software GmbH Windows CODEWRIGHT Borland Software Corporation Windows CODE CONFIDENCE TOOLS Code Confidence Ltd Windows CODE CONFIDENCE ...

Page 46: ...BVIEW NATIONAL INSTRUMENTS Corporation Windows TPT PikeTec GmbH Windows CANTATA QA Systems Ltd Windows RAPITIME Rapita Systems Ltd Windows TESSY Razorcat Development GmbH Windows DA C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows ECU TEST TraceTronic GmbH Windows UNDODB Undo Software Linux TA INSPECTOR Vector Windows VECTORCAST UNIT TESTING Vector Software Windows VECTORCAST CODE COVER...

Page 47: ...6560 80C515 12 0 12 0 12 0 12 0 12 0 12 0 LA 6568 80C515A 18 0 18 0 18 0 18 0 18 0 18 0 LA 6560 80C517 12 0 12 0 12 0 12 0 12 0 12 0 LA 6567 80C517A 18 0 18 0 18 0 18 0 18 0 18 0 LA 6510 80C51FA 16 0 16 0 16 0 16 0 16 0 16 0 LA 6522 80C51GB 16 0 16 0 16 0 16 0 16 0 16 0 LA 6510 80C51RA 24 0 24 0 24 0 24 0 24 0 24 0 LA 6550 80C52 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 80C52T2 16 0 16 0 16 0 16 0 16 ...

Page 48: ...782 12 0 12 0 12 0 12 0 12 0 12 0 LA 6512 87C51 12 0 12 0 12 0 12 0 12 0 12 0 LA 6550 87C52 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 87C552 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 87C652 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 87C654 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 89C851 16 0 16 0 16 0 16 0 16 0 16 0 LA 6550 AT89C51 16 0 16 0 16 0 16 0 16 0 16 0 LA 6570 C501 18 0 18 0 18 0 18 0 18 0 18 0 LA 6510 C...

Page 49: ...DIL40 80C321 DIL40 80C32T2 DIL40 80C51 DIL40 80C51FA DIL40 80C51RA DIL40 80C652 DIL40 80C662 DIL40 80C851 DIL40 80CL410 DIL40 80CL410 PLCC44 8344 DIL40 83C51FB DIL40 83C528 DIL40 83C550 DIL40 87C51 DIL40 87C52 DIL40 C501 DIL40 C502 DIL40 LA 6510 8031 PLCC44 8032 PLCC44 8051 PLCC44 8052 PLCC44 80C154 PLCC44 80C31 PLCC44 80C32 PLCC44 LA 6520 LA 6500 ...

Page 50: ...4 83C154 PLCC44 83C51FB PLCC44 83C528 PLCC44 83C550 PLCC44 87C51 PLCC44 87C52 PLCC44 C501 PLCC44 C502 PLCC44 C504 PLCC44 COM20051 PLCC44 LA 6520 80C51GB PLCC68 LA 6522 80C152JA DIL48 80C152JA PLCC68 80C152JB PLCC68 80C152JC DIL48 80C152JC PLCC68 80C152JD PLCC68 LA 6530 LA 6530 80C154 DIL40 80C31 DIL40 80C52 DIL40 83C154 DIL40 87C51 DIL40 LA 6512 80C552 PLCC68 LA 6549 LA 6500 ...

Page 51: ...80C652 PLCC44 83C652 DIL40 83C652 PLCC44 83C654 DIL40 83C654 PLCC44 83C851 DIL40 83C851 PLCC44 87C51 DIL40 87C51 PLCC44 87C52 DIL40 87C52 PLCC44 87C652 DIL40 87C652 PLCC44 87C654 DIL40 87C654 PLCC44 89C851 DIL40 89C851 PLCC44 AT89C51 DIL40 AT89C51 PLCC44 LA 6552 LA 6550 80C592 PLCC68 83C592 PLCC68 LA 6555 80C515 PLCC68 83C515B 4 PLCC68 LA 6561 80C517 PLCC84 80C537 PLCC84 LA 6562 LA 6560 LA 6500 ...

Page 52: ...7A PLCC84 LA 6562 C501 DIL40 C501 PLCC44 C502 DIL40 C502 PLCC44 LA 6563 C503 PLCC44 LA 6564 LA 6570 80C515 PLCC68 LA 6565 80C517 PLCC84 LA 6566 C515C ET80 QF14 LA 6578 80C517A PLCC84 LA 6567 80C515A PLCC68 83C515B 4 PLCC68 LA 6568 C503 PLCC44 LA 6575 83CL782 DIL40 LA 6582 83CL580 QFP64 83CL580 VSO56 LA 6584 LA 6580 LA 6500 ...

Page 53: ...ICE Emulator for 8051 53 1989 2019 Lauterbach GmbH Order Information ...

Page 54: ...CE Emulator for 8051 54 1989 2019 Lauterbach GmbH Physical Dimensions Dimension LA 6510 M 8051 DIL40 cable 400 53 78 SIDE VIEW 25 6 26 9 73 dimensions define position of socket to target 16 12 TOP VIEW 1 ...

Page 55: ...ICE Emulator for 8051 55 1989 2019 Lauterbach GmbH LA 6520 M 8051 PLCC Dimension cable 400 53 26 77 SIDE VIEW 24 73 dimensions define position of socket to target 1 16 15 TOP VIEW ...

Page 56: ...ICE Emulator for 8051 56 1989 2019 Lauterbach GmbH LA 6522 M 8051GB PLCC Dimension cable 400 75 24 95 SIDE VIEW 9 26 20 73 23 13 44 dimensions define position of socket to target 1 TOP VIEW ...

Page 57: ...ICE Emulator for 8051 57 1989 2019 Lauterbach GmbH LA 6530 M 80152 JA JB Dimension cable 400 71 37 13 27 68 94 SIDE VIEW 80C152JB TOP VIEW 73 16 11 44 31 12 3 1 ...

Page 58: ...ICE Emulator for 8051 58 1989 2019 Lauterbach GmbH LA 6512 M 80154 DIL40 Dimension 53 80154 Piggy B cable 400 18 80 SIDE VIEW 24 6 11 73 dimensions define position of socket to target 11 20 TOP VIEW ...

Page 59: ...ICE Emulator for 8051 59 1989 2019 Lauterbach GmbH LA 6514 M 80154 PLCC Dimension 53 80154 Piggy B cable 400 18 80 SIDE VIEW 24 26 9 25 73 dimensions define position of socket to target 26 19 TOP VIEW 1 ...

Page 60: ...ICE Emulator for 8051 60 1989 2019 Lauterbach GmbH LA 6550 M 80582 B Dimension cable 400 73 80C582E 37 13 72 98 SIDE VIEW 9 26 1 73 30 22 21 TOP VIEW ...

Page 61: ...ICE Emulator for 8051 61 1989 2019 Lauterbach GmbH LA 6551 A 80582 C552 Dimension 13 72 SIDE VIEW 9 26 1 73 30 22 21 TOP VIEW all dimension in mm ...

Page 62: ...ICE Emulator for 8051 62 1989 2019 Lauterbach GmbH LA 6552 A 80582 C652 Dimension 72 SIDE VIEW 9 26 13 1 73 26 TOP VIEW all dimension in mm 24 16 44 12 12 ...

Page 63: ...ICE Emulator for 8051 63 1989 2019 Lauterbach GmbH LA 6555 M 80592 Dimension cable 400 75 25 26 95 SIDE VIEW 73 14 dimensions define position of socket to target 1 23 20 TOP VIEW ...

Page 64: ...ICE Emulator for 8051 64 1989 2019 Lauterbach GmbH LA 6560 M 80517 Dimension cable 400 71 80C515 7 Bondout 37 13 10 26 68 94 SIDE VIEW TOP VIEW 1 30 36 ...

Page 65: ...ICE Emulator for 8051 65 1989 2019 Lauterbach GmbH LA 6570 M 80517A Dimension cable 400 71 80C517A Bondout 37 13 10 26 68 94 SIDE VIEW TOP VIEW 1 30 36 ...

Page 66: ...ICE Emulator for 8051 66 1989 2019 Lauterbach GmbH LA 6561 A 80517 515 Dimension 13 10 26 68 SIDE VIEW TOP VIEW all dimension in mm 1 30 36 73 ...

Page 67: ...ICE Emulator for 8051 67 1989 2019 Lauterbach GmbH LA 6562 A 80517 517 Dimension 13 9 26 68 SIDE VIEW 12 TOP VIEW all dimension in mm 1 18 18 73 ...

Page 68: ...ICE Emulator for 8051 68 1989 2019 Lauterbach GmbH LA 6563 A 80517 C502 Dimension 13 9 26 68 SIDE VIEW 32 12 TOP VIEW all dimension in mm 1 PIN 1 25 25 11 11 73 ...

Page 69: ...ICE Emulator for 8051 69 1989 2019 Lauterbach GmbH LA 6564 A 80C517 C503 Dimension 13 10 26 68 SIDE VIEW TOP VIEW all dimension in mm 1 33 38 73 ...

Page 70: ...ICE Emulator for 8051 70 1989 2019 Lauterbach GmbH LA 6565 M 80535 PLCC Dimension cable 400 75 CPU 95 SIDE VIEW 25 26 dimensions define position of socket to target 1 73 13 20 23 TOP VIEW ...

Page 71: ...ICE Emulator for 8051 71 1989 2019 Lauterbach GmbH LA 6566 M 80537 PLCC Dimension cable 400 75 38 73 94 SIDE VIEW 25 dimensions define position of socket to target 1 73 17 21 TOP VIEW ...

Page 72: ...ICE Emulator for 8051 72 1989 2019 Lauterbach GmbH LA 6578 M C515C Dimension cable 400 76 7 96 SIDE VIEW 24 81 dimensions define position of socket to target 13 9 TOP VIEW 1 ...

Page 73: ...ICE Emulator for 8051 73 1989 2019 Lauterbach GmbH LA 6567 M 83517A PLCC Dimension cable 400 75 38 73 94 SIDE VIEW 24 dimensions define position of socket to target 1 73 17 21 TOP VIEW ...

Page 74: ...ICE Emulator for 8051 74 1989 2019 Lauterbach GmbH LA 6568 M 83515A PLCC Dimension cable 400 75 CPU 95 SIDE VIEW 24 26 dimensions define position of socket to target 1 73 14 20 23 TOP VIEW ...

Page 75: ...ICE Emulator for 8051 75 1989 2019 Lauterbach GmbH LA 6575 M C503 PLCC Dimension cable 400 71 24 95 SIDE VIEW 26 24 73 26 17 41 dimensions define position of socket to target 1 TOP VIEW ...

Page 76: ...ICE Emulator for 8051 76 1989 2019 Lauterbach GmbH LA 6580 M 85CL000 Dimension cable 400 69 24 13 67 93 SIDE VIEW 6 75 PIN 1 50 32 11 13 TOP VIEW ...

Page 77: ...ICE Emulator for 8051 77 1989 2019 Lauterbach GmbH LA 6582 A 85CL782 Dimension 13 67 SIDE VIEW 6 75 PIN 1 50 32 11 13 TOP VIEW all dimension in mm ...

Page 78: ...ICE Emulator for 8051 78 1989 2019 Lauterbach GmbH LA 6584 A 85CL580 Dimension 6 8 30 27 13 24 54 75 TOP VIEW all dimension in mm SIDE VIEW 66 9 ...

Page 79: ...lator for 8051 79 1989 2019 Lauterbach GmbH Adapter Socket CPU Adapter ET80 QF14 C515C YA 1131 ET80 EYA QF14 Emul Adapter for YAMAICHI socket ET080 QF14 6 66 SIDE VIEW 8 51 11 18 TOP VIEW all dimensions in mm ...

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