Lattice MIPI D-PHY, User Manual

Page: 5 / 28

MIPI D-PHY Bandwidth Matrix Table
User Guide
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02041-1.1 5
1. Introduction
As we move from the world of standard-definition to the high-definition and ultra-high-definition, the common parallel
interfaces are difficult to expand, require many interconnects and consume relatively large amounts of power.
Emerging packet-based serial interfaces, such as MIPI CSI-2 and DSI address many of the shortcomings of the parallel
interfaces, while also introducing system complexity. Understanding the mathematics behind the parallel and serial
interface bandwidth estimation can prevent a lot of problems when choosing an FPGA device with the right number of
data lanes supporting the required data transfer rate. This document describes in details the methods of calculating the
bandwidth and data rate of the image sensor’s output of the RGB, YUV, or RAW data over a single or multi-lane MIPI
CSI-2 and DSI interface. The same calculation method can be applied to other video interface such as FPD-Link, HiSPI,
and HDMI.
Figure 1.1 shows a conceptual model of the CMOS Sensor Bridge Design. On the left, a CMOS sensor transfers image
data to the FPGA through 1 to 4 serial data lanes; the FPGA sensor bridge merges the image data from multiple lanes
and converts them into parallel data; on the right, the image data are sent out over the parallel bus in standard video
format. Based on the known video format information, we can calculate the required bandwidth. Because the FPGA
does not buffer the video frames, the peak transfer rate of CMOS sensor input must meet the bandwidth requirement
of the output. With this presumption, we can estimate the maximum data rate and bit clock frequency of the CMOS
sensor interface.
Figure 1.1. CMOS Sensor Bridge Model