Lattice Semiconductor MachXO5-NX Development Kit, User Manual

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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12 FPGA-EB-02052-0.90
3. Hard JTAG/I
2
C Programming
The hardened JTAG/I
2
C programming architecture of the MachXO5-NX Development Board is shown in Figure 3.1 . The
board has a built-in download controller for programming the MachXO5-25 device. It uses an FT2232H Future
Technology Devices International (FTDI) part U1 to convert USB to JTAG from port A, or convert USB to I
2
C from port B.
Using Detect Cable function with Radiant programming software installed, you can detect dual ports after power up
the board and connect the mini USB to USB-A cable from J11 to your PC ensuring FTDI reset control jumper JP9 is not
populated as default. The software select option FTUSB-0 is dedicate for hard JTAG and FTUSB-1 is dedicate for hard I
2
C
which is mapping with port A and port B from hardware perspective, as shown in Figure 3.2 .
Mini-USB
(J11)
USB
FT2232H
(U1)
Port A
Port B
MachXO5-NX (U3)
Lev el
Shift
(U14)
rst#
JP9
GND
FTDI_SCL
FTDI_SDA
SCL0
SDA0
JP12
JP13
TDI
TCK
TMS
TDO
NX_TDI
NX_TCK
NX_TMS
NX_TDO
OEN
Config JTAG Header (J1)
JP1
3.3V
Figure 3.1. JTAG/I
2
C Programming Architecture
Figure 3.2. Radiant Programmer Detect Dual Ports
3.1. JTAG Download Interface
A level shifter SN74AVC4T774 U14 from TI is inserted between Config FTDI Port A and MachXO5-25 JTAG port to make
sure the FTDI fixed I/O voltage can adapt with flexible voltage selection of FPGA’s bank 2, as shown in
Figure 3.3 . An
8-pin header J1 as shown in Figure 3.4 allowing you not only to probe the JTAG signals, but also to access MachXO5-25
JTAG port from external JTAG host such as external Lattice HW-USBN-2B Programming Cable (available separately), or
access SSPI port from external SPI host. In those cases, jumper JP1 must be added to pull OEN high and ensure U14 to