7
MachXO Starter Evaluation Board
Lattice Semiconductor
User’s Guide
Prototype Area
The MachXO Starter Evaluation Board contains a 0.8” x 1.0” plated through hole prototype area. The holes are
spaced on 0.1” centers and are not connected to any MachXO device pins.
Programming Headers
A 1x10 programming header is provided on the MachXO Starter Evaluation Board, providing access to the
MachXO JTAG port. The header is compatible with all Lattice ispDOWNLOAD cables. The pinout for the header is
provided in Table 4.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-
erable.
An ispDOWNLOAD cable is included with purchase of the ispLEVER design tools. Cables may also be purchased
separately from Lattice. Visit the Lattice web store to learn more at: www.latticesemi.com/store.
Table 4. JTAG Programming Header Connections
Power Setup
Power is supplied to the PCB via the supplied 5V AC/DC transformer. The DC input jack is a 2.5mm, positive tip
size connector. Input voltage should not exceed 9V DC. 800mA low dropout regulators provide V
CC
core and V
CCIO
voltages. The adjustable voltage regulator output can be modified by changing the value of resistor R153. The
equation for calculating V
ADJ
is as follows:
V
ADJ
= 1.25 * (1 + R2/120)
Table 5 shows some common voltages, and the appropriate resistor value for setting each voltage. Resistance
given is for the closest standard value. Resistor pads are 0805 component size.
JTAG Programming
Function
JP1 Pin Number (1x10)
Mach XO Device Pin
Expansion Connector Pin
+3.3V
1
N/A
N/A
TDO
2
31
J1-34
TDI
3
33
J1-35
N/C
4
N/A
N/A
N/C
5
N/A
N/A
TMS
1
6
26
J1-33
GND
7
N/A
N/A
TCK
1
8
28
J1-32
N/C
9
N/A
N/A
N/C
10
N/A
N/A
1. Please note that some versions of the MachXO Starter Evaluation Board may have an incorrect silkscreen marking for these pins on the
printed circuit board. Please follow the connections guidelines in Table 4, and not the silkscreen markings on the board.
