Timing Diagrams
LatticeMico GPIO
13
Figure 6 shows how the GPIO’s master ports read the data in the internal
register.
Figure 7 shows how the GPIO generates interrupt requests when a signal is
high or low.
Figure 8 shows how the GPIO generates interrupt requests when the
PIO_DATA signal transitions from low to high. After an edge is detected, the
Edge_Capture bit is held at a 1 until cleared in the IRQ_MASK register.
Figure 6: WISHBONE Master Reads Data in the Internal Register
Figure 7: IRQ Generation (Level)
