7
ispMACH 4256ZE Breakout Board
Evaluation Kit User’s Guide
USB port or optionally with external power. You may create or modify CPLD program files using ispLEVER Classic
software and reprogram the board using ispVM software.
Figure 3. ispMACH 4000ZE Breakout Board Block Diagram
ispMACH4256ZE-5T
N144C
2x20 Header
Landing (J3)
LED
Array
20 GPIO
USB
Controller
USB Mini B
Socket
A/Mini-B
USB Cable
JTAG
Programming
8
2x20 Header
Landing (J4)
35 GPIO
2x20 Header
Landing (J5)
40 GPIO
2x20 Header
Landing (J6)
15 GPIO
1x8 JTAG Header
Landing (J1)
8
Table 1 describes the components on the board and the interfaces it supports.
Table 1. Breakout Board Components and Interfaces
Component/Interface
Type
Schematic Reference
Description
Circuits
USB Controller
Circuit
U2: FT2232H
USB-to-JTAG interface and dual USB UART/FIFO IC
USB Mini-B
Socket
I/O
J1:USB_MINI_B
Programming and debug interface
Components
LC4256ZE
CPLD
U4: LC4256ZE-5TN144C
256-macrocell CPLD packaged in a 20 x 20mm,
144-pin TQFP
Interfaces
LED Array
Output
D8-D1
Red LEDs
Four 2x20 header landings
I/O
J3: header_2x20
J4: header_2x20
J5: header_2x20
J6: header_2x20
User-definable I/O
1x8 header landing
I/O
J1: header_1x8
Optional JTAG interface
4x15 prototype area
J9
Prototype area 100mil centered holes
Subsystems
This section describes the principle subsystems for the ispMACH 4256ZE Breakout Board in alphabetical order.
Clock Sources
All clocks for the counter demonstration designs originate from the ispMACH 4256ZE CPLD on-chip oscillator and
timer (OSCTIMER) block. You may use an expansion header landing to drive a CPLD input with an external clock
source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and Bank 0/1 VCCO pins of
the ispMACH 4256ZE. The remaining pins serve as power supplies for external connections. Each landing is con-
figured as one 2x20 100 mil.
Table 2. Expansion Connector Reference
Item
Description
Reference Designators
J3, J4, J5, J6
Part Number
header_2x20
