Lattice Semiconductor ispLever Core Multi-Channel DMA Controller, User Manual, Page: 16 / 29

Lattice Semiconductor Multi-Channel DMA Controller User’s Guide
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Figure 5 shows the timing waveform for two words DMA transfer.
Figure 5. Two Word DMA Transfer Timing Waveform
Clock
dreq
hreq
Si S0
S0
S1
S2 S3 S4
aen
aout
dack
iorout_n/memr_n
S2
S3 S4
Valid Address
Note 1.
iowout_n/memw_n
hlda
Valid Address
Si
Note 1. This timing diagram demonstrates the extended write operation. In the 8237 mode, when normal write operation is
selected,
iowout_n or the memw_n is asserted one clock cycle later.
If compressed timing is selected, the state S3 is bypassed, making the read and write pulses of equal width. This is only
applicable in 8237 mode.
The iowout_n and memw_n signals are generated off the falling clock edge. This ensures the address is held at least for
half a cycle after the rising edge of the write signal.