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Lattice Semiconductor ECP5 Versa, Technical Note

The Lattice Semiconductor ECP5 Versa is a versatile FPGA development board that offers advanced features for those looking to design and prototype their projects. With a user-friendly interface and extensive capabilities, users can easily get started with the Quick Start Manual available for free download at manualshive.com.

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ECP5 and ECP5-5G High-Speed I/O Interface 

 

Technical Note 
 

© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

36 

 

 

FPGA-TN-02035-1.3 

6.2.4.

 

READ Pulse Positioning Optimization 

The memory controller is required to provide the READ1/0 signal to the DQSBUF block to position the internal READ 
pulse and generate the DATAVALID output that indicates the proper timing window of the valid read data. The internal 
READ pulse is also used to get a clean internal DQS signal between the preamble and postamble periods. The clean DQS 
is 90° shifted internally to be used to capture the read data. 

Due to the DQS round trip delay that includes PCB routing and I/O pad delays, proper positioning of the READ pulse is 
crucial for successful read operations. The ECP5 and ECP5-5G device DQSBUF block provides the dynamic READ pulse 
positioning function which allows the memory controller to locate the READ pulse to an appropriate timing window for 
the read operations by monitoring the positioning result. 

The READCLKSEL2/1/0 and BURSTDET signals are used to accomplish the READ pulse positioning function for a 
corresponding DQSBUF block. The READ1/0, READCLKSEL2/1/0 signals are driven by the user logic and are part of the 
DDR memory controller. 

The READ1/0 signal needs to be asserted high a certain amount of time before the read preamble starts. The suggested 
READ1/0 signal assertion timing and the required duration of assertion are listed in 

Table 6.3

. When the internal READ 

pulse is properly positioned, BURSTDET is asserted high and guarantee that the generated DATAVALID signal properly 
indicates the valid read data time window. The READ1/0 signal must stay asserted as long as the number of SCLK cycles 
that is equal to one fourth of the total burst length as listed in the 

Table 6.3

. 

Table 6.3. DDRDLL Connectivity 

Gearing Mode 

READ Control 

DQSBUF Block 

Initial READ Assertion Position

*

 

READ Width in SCLK 

X2 Gearing 
(All DDR Memory Interfaces) 

READ1 
READ0 

READCLKSEL2 
READCLKSEL1 
READCLKSEL0 

DQSBUFM 

At least 5.5T before preamble 

Total Burst Length/4 

*

Note

: Subject to change after validation tests. The number shown does not include DQS round trip delay. 

1T = 1 tCK memory clock cycle 

Once the controller initially positions the internal READ pulse using the READ1/0 and READCLKSEL2/1/0 signals, 
BURSTDET can be used to monitor the positioning result to optimize the READ pulse position. The BURSTDET signal 
provides a feedback mechanism to inform the memory controller whether the READ pulse has reached to the optimal 
position for the read operations or not with the current READ1/0 and READCLKSEL2/1/0 values. When it reaches to the 
optimal position, BURSTDET is asserted High after a read operation. Otherwise, BURSTDET remains Low. A minimum 
burst length of eight on the memory bus must be used in the training process. This can be done either with two 
consecutive BL4 (BL=4) read accesses or one BL8 read access. Any even number of BL4, or any multiplication of 
BL8(BL=8) can also be used. This read pulse training process must be performed during the initial training and can also 
be periodically calibrated during the normal operations. 

The BURSTDET signal is asserted after the last DQS transition is completed during a read operation and lasts until the 
next read cycle is started. Once a read operation is started, the memory controller should wait until the DATAVALID 
signal from DQSBUFM is asserted and then sample the BURSTDET signal at the next cycle to monitor the READ pulse 
positioning result. If there is no assertion on BURSTDET, it means that the READ pulse has not been located to the 
optimal position yet. Then, the memory controller needs to shift the READ1/0 signal and/or increase the 
READCLKSEL2/1/0 value until it detects a BURSTDET assertion. It is recommended that at least 128 read operations be 
performed repetitively at a READ pulse position during the initialization for getting jitter immunity. 16 read operations 
can be performed in a periodic calibration if used during the normal operation. The memory controller can determine 
the proper position alignment when there is no failure on BURSTDET assertions during these multiple trials. 

To reposition the internal READ pulse: 

1.

 

The memory controller sets READ1/0 to an initial position before starting the read pulse training. READ1/0 must be 
asserted for the number of SCLK cycles that is equal to one-fourth of the current read burst length as listed in 

Table 

6.3

. Each READ bit (READ1 or READ0) in the system clock domain is translated to an 1T time slot of the memory 

clock domain as shown in 

Figure 6.7

. 

Summary of Contents for ECP5 Versa

Page 1: ...ECP5 and ECP5 5G High Speed I O Interface Technical Note FPGA TN 02035 1 3 October 2020...

Page 2: ...and with all faults and all risk associated with such information is entirely with Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by...

Page 3: ...RX2_RX MIPI 20 5 6 GDDRX71_RX ECLK 21 5 7 GDDRX1_TX SCLK Aligned 22 5 8 GDDRX1_TX SCLK Centered 22 5 9 GDDRX2_TX ECLK Aligned 23 5 10 GDDRX2_TX ECLK Centered 24 5 11 GDDRX71_TX ECLK 25 5 12 Generic DD...

Page 4: ...ic modules 53 7 4 Configuring 7 1 LVDS Interface Modules 57 7 5 Configuring DDR Memory Interfaces 58 7 6 Building DDR Interfaces in Clarity Designer 62 7 7 Planning DDR Interfaces in Clarity Designer...

Page 5: ...nd disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein...

Page 6: ...Figure 5 18 tCO Min and Max Timing Analysis 29 Figure 5 19 Transmit Centered Interface Timing 29 Figure 5 20 Transmit Aligned Interface Timing 30 Figure 6 1 Typical DDR2 DDR3 DDR3L Memory Interface 31...

Page 7: ...Figure 8 3 DDRDLLA Primitive 66 Figure 8 4 DLLDELD Primitive 67 Figure 8 5 IDDDRX1F Primitive 68 Figure 8 6 IDDRX2F Primitive 69 Figure 8 7 IDDR71B 69 Figure 8 8 ODDRX1F 70 Figure 8 9 ODDRX2F 70 Figur...

Page 8: ...nd Parameters 61 Table 7 8 DDR_MEM Advanced Settings Tab Parameters 62 Table 8 1 Software Primitives 64 Table 8 2 DELAYF Port List 65 Table 8 3 DELAYG Port List 65 Table 8 4 DELAYF and DELAYG Attribut...

Page 9: ...r respective holders The specifications and information herein are subject to change without notice FPGA TN 02035 1 3 9 Acronyms in This Document A list of acronyms used in this document Acronym Defin...

Page 10: ...PDDR2 and LPDDR3 SDRAM memory interfaces This document discusses how to utilize the capabilities of the ECP5 and ECP5 5G devices to implement high speed generic DDR interface and the DDR memory interf...

Page 11: ...and ECP5 5G sysClock PLL DLL Design and Usage Guide FPGA TN 02200 Below is a brief description of each of the major elements used for building various high speed interfaces The DDR Software Primitive...

Page 12: ...the input clock There is one DDRDLL at each corner of the device totaling to four DDRDLLs on each device The DDRDLL on the top corners of the device can drive delay codes to two adjacent edges of the...

Page 13: ...ed 7 1 interface the IDDR element inputs a single DDR data input and ECLK and output a 7 bit wide parallel data synchronized to SCLK primary clock to the FPGA fabric 3 9 Output DDR ODDR The output DDR...

Page 14: ...ntered in data window Receive DDRX2 Aligned GDDRX2_RX ECLK Aligned DDR x2 Input using ECLK Data is edge to edge with incoming clock Generic DDR X2 using Edge Clock DLLDEL is be used to shift the incom...

Page 15: ...signer Some of these are mandatory for the module to function as expected and are automatically generated when building the interface through Clarity Designer 5 1 GDDRX1_RX SCLK Centered This a Generi...

Page 16: ...esigner DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the correct delay value can be set in the delay element Dynamic Margin adjustment in the DDRDLL...

Page 17: ...Edge Clock Tree ECLK Input clock is centered to the input data This interface must be used for speeds above 400 MHz This DDR interface uses the following modules IDDRX2F element for X2 mode to captur...

Page 18: ...se the Primary Clock tree software errors out if these dedicated clock routes are not used USE PRIMARY preference may be assigned to the SCLK net You must set the timing preferences as indicated in th...

Page 19: ...he following figures show the static delay and dynamic delay options for this interface Datain Clkin A DELAYG Z DLLDELD Z A DDRDEL LOADN MOVE DIRECTION CFLAG CLK RST UDDCNTLN FREEZE DDRDEL LOCK DDRDLL...

Page 20: ...eed modes The HSSEL of IMIPI should be driven by a soft IP When in high speed mode The OHSOLS1 of the element is active The OHSOLS1 of the data IMIPI element is connected to the data input GDDRX2_RX E...

Page 21: ...arity Designer The Bit alignment module rotates PLL s 16 phases to center Edge Clock to middle of data eye and the word alignment module uses ALIGNWD function of CLKDIVD and IDDRX71B to achieve 7 bit...

Page 22: ...you can choose to use the DELAYG or DELAYF element to delay the output data The output data can be optionally tristated using either a Tristate input going through an I O register Figure 5 11 GDDRX1_T...

Page 23: ...ECLK is routed to the Edge Clock tree through the ECLKSYNCB module The SCLK is routed on the primary clock tree and is generated from the ECLK using the CLKDIVF module The same ECLK and SCLK are used...

Page 24: ...ed to generate the clocks for the data and clock ODDR modules The clock used to generate the clock output is delayed 90 to center to data at the output The startup synchronization soft IP GDDRX_SYNC i...

Page 25: ...an be enabled through Clarity Designer SCLK RST Q ODDRX71B Data0 6 0 SCLK RST Q 7 b1100011 Dout Clkout ECLK ECLKI STOP ECLKO CLKDIVF CLKI RST ALIGNWD CDIVX D 6 0 ECLK divby 3 5 Edge Primary Sclk Refcl...

Page 26: ...interface Guidelines Use PADA and PADB for all TX using true LVDS interfaces When implementing Transmit Centered interface two ECLKs are required One is to generate the data output and the other is to...

Page 27: ...he design This preference may not be required if the clock is generated out of a PLL or DLL or is input to a PLL or DLL 5 13 2 DDR Input Setup and Hold Time Constraints All of the Receive RX interface...

Page 28: ...PGA DS 02012 specifies the MIN tDVA_GDDRX1 2 and tDVE_GDDRX1 2 values required for each of the high speed interfaces running at MAX speed These values can be picked up from the data sheet if the inter...

Page 29: ...n t U t DVBCKGDDR t DVACKGDDR t DVACKGDDR t DVBCKGDDR T Target Edge CLK DATA Figure 5 19 Transmit Centered Interface Timing Figure 5 19 shows that max value after which the data cannot transition is t...

Page 30: ...e timing diagram for this interface tDIAGDDR Data valid after clock tDIBGDDR Data valid before clock Transmit Parameters CLK Data TDAT TCTL tDIAGDDR tDIBGDDR tDIBGDDR tDIAGDDR Figure 5 20 Transmit Ali...

Page 31: ...iations The memory also uses these clock signals to generate the DQS signal during a read via a DLL inside the memory The figures below show DQ and DQS timing relationships for read and write cycles D...

Page 32: ...FPGA TN 02035 1 3 FPGA DDR Memory Controller DQ 7 0 DQS DQS DM CA 9 0 CSN CKE ODT LPDDR3 CK CK DDR Memory 8 10 DQ 7 0 DQS DQS DM CA 9 0 CSN CKE ODT LPDDR3 CK CK DQ 7 0 DQS DQS DM CA 9 0 CSN CKE ODT CK...

Page 33: ...peed operation When reading data from the external memory device data coming into the ECP5 and ECP5 5G device is edge aligned with respect to the DQS signal Therefore the ECP5 and ECP5 5G device needs...

Page 34: ...nd ECP5 5G devices support DQS signals on the left and right sides of the device Each DQS signal spans across 12 to 16 I O Any 10 for DDR2 or 11 for DDR2 DDR3 LPDDR2 LPDDR3 of these 16 I O spanned by...

Page 35: ...ble 6 2 DDRDLL Connectivity DDRDLL Location Left DQSBUFs Right DQSBUFs DDRDLL_TR X DDRDLL_TL X DDRDLL_BR X DDRDLL_BL X The DQS received from the memory is delayed in the DQS delay element in the DQSBU...

Page 36: ...Note Subject to change after validation tests The number shown does not include DQS round trip delay 1T 1 tCK memory clock cycle Once the controller initially positions the internal READ pulse using...

Page 37: ...T timing it is recommended that both READ1 and READ0 are moved to the next cycle together to shift the READ pulse to the next 2T window as the example shown in Figure 6 7 Repeat step 2 and step 3 unti...

Page 38: ...uous DQS domain to the continuous ECLK The FIFO is written by the DQS strobe and read back by ECLK which has the identical frequency rate as DQS The input FIFO also performs the read leveling function...

Page 39: ...on_0 rdcflag_0 wrcflag_0 datavalid_0 burstdet_0 IDDRX2DQA Figure 6 8 DDR2 DDR3 DDR3L LPDDR2 and LPDDR3 Read Side Implementation The read side is implemented using the following software elements DDRX2...

Page 40: ...arity Designer When using ECLKBRIDGECS there are two DDRDLLs in the design one for each side Also the DQSBUFMs used on the second side should be connected to its DDRDLL Clarity Designer automatically...

Page 41: ...he ODDRX2 module before data is transferred to the DQSW270 and DQSW clocks The ECLK is generated by the EHXPLLL module and the SCLK is generated by the CLKDIVF module both shown in the Read side imple...

Page 42: ...nd 1 is used to generate the CLKP CLKN outputs On LPDDR3 even the ODT has D0 and D1 tied together and D2 and D3 tied together and uses same DQSBUFM The DQSBUFM used for CA requires a separate input Id...

Page 43: ...DDR_reset Sclk from CLKDIVF as shown in the Input interface Eclk from ECLKSYNCB as shown in the Input interface DQSR 90 WRPNTR 2 0 RDPNTR 2 0 SCLK RST DQSW 270 ECLK DQSW D0 D1 RST DQSW D2 D3 SCLK ECLK...

Page 44: ...he device does not support DQSBUF blocks As such it does not support DDR memory interfaces Although some of the ADDR CMD generation that uses ODDRX1 modules can be placed on the top side of the device...

Page 45: ...following sections are the general termination guideline for the ECP5 and ECP5 5G device DDR memory interface 6 5 1 Termination for DQ DQS and DM Do not locate any termination on the memory side The m...

Page 46: ...VTT on address command and control signals at the memory side because the DIMM already has termination on the module Follow the termination for DQ DQS and DM guideline above for the FPGA side terminat...

Page 47: ...cate a spacer DQS group between the data DQS groups if possible A DQS group becomes a spacer DQS group if the I O pads inside the group are not used as data pads DQ DQS DM In DDR2 DDR3 and DDR3 the pa...

Page 48: ...a pseudo powerm pad is located If the data DQS group includes VREF1 locate DM to the other side of VREF with respect to DQS It can be used as an isolator due to its almost static nature in most applic...

Page 49: ...nterfaces In addition to building and planning Clarity Designer can be used to build top level modules by connecting the modules together in the Builder For step by step assistance with Clarity please...

Page 50: ...ted under Architecture Modules I O This includes SDR Select to build SDR Modules DDR_GENERIC Select to build any DDR Generic Receive and Transmit Interfaces GDDR_7 1 Select to build 7 1 LVDS Receiver...

Page 51: ...isted at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change...

Page 52: ...from the clock frequency entered Calculated Calculated Interface Interface selected based on previous entries Transmit GOREG_TX SCLK Receive GIREG_RX SCLK default GIREG_RX SCLK Clock Inversion Option...

Page 53: ...gner Enter the name of the module Figure 7 4 shows the type of interface selected as DDR_Generic and module name entered This module can then be configured by clicking the Customize button Figure 7 4...

Page 54: ...Output Standards Enable Tristate Control Enabled Disabled Bus Width for this Interface 1 256 Clock Frequency for this Interface 3 125 400 MHz 200 400 MHz or Receive MIPI Interface Bandwidth Calculated...

Page 55: ...choose to set it By Lane where all the parallel data bits from each lane are organized together in the data output If By Time is chosen instead a single bit from each of the data lanes is put togethe...

Page 56: ...MOS25 Enable MIPI Filter Soft IP for Low Speed Data Generates the MIPI Filter soft IP in module for Interface Receiver MIPI Enable Disable Disable Table 7 4 shows how the interfaces are selected by Cl...

Page 57: ...ring 7 1 LVDS Interface Modules To build a 7 1 LVDS DDR interface select GDDR_7 1 option under Architecture Modules I O in the Catalog tab of Clarity Designer Enter the name of the module Figure 7 7 s...

Page 58: ...r 1 channel of 7 1 LVDS interface 1 16 Clock Frequency Pixel clock speed 3 125 MHz 108 MHz Enable Bit Alignment and Word Alignment Soft IP included with the module to implement Bit and Word alignment...

Page 59: ...laimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are su...

Page 60: ...ot user selectable display only SCLK Frequency Value DDR Memory Frequency 2 Data Width DDR memory interface data width DDR2 DDR3 DDR3L 8 16 24 32 40 48 56 64 72 LPDDR2 LPDDR3 16 32 16 Number of DQ per...

Page 61: ...s Table 7 7 DDR_MEM Clock Address Command Parameters User Interface Option Range Default Value Number of Clocks DDR2 1 2 4 DDR3 1 2 4 DDR3L 1 2 4 LPDDR2 1 LPDDR3 1 DDR3 1 DDR2 1 DDR3L 1 LPDDR2 1 LPDDR...

Page 62: ...ent FACTORYONLY PLUS MINUS FACTORYONLY DQS Read Delay Value Grey out if DQS Delay Adjustment FACTORYONLY 0 255 if DQS delay adjustment PLUS 1 256 If DQS delay Adjustment MINUS DQS Write Delay Adjustme...

Page 63: ...t DDR interface at the selected location The planner takes into account all the clocking and placement requirements any architecture limitations for each type DDR interface If any of the placement rul...

Page 64: ...F Generic DDR 2x gearing registers ODDR71B Generic DDR 7 1 gearing registers shared by two I O LOGIC blocks DDR Memory DQSBUF Control DQSBUFM Used to phase shift DQS Strobe signal and generate control...

Page 65: ...F LOADN MOVE DIRECTION Z CFLAG Figure 8 1 DELAYF Primitive Table 8 2 DELAYF Port List Port I O Description A I Data input from pin or output register block LOADN I 0 on LOADN resets to default delay s...

Page 66: ...LK_ZEROHOLD ECLK_ALIGNED ECLK_CENTERED SCLK_ALIGNED SCLK_CENTERED ECLKBRIDGE_ALIGNED ECLKBRIDGE_CENTER ED DQS_CMD_CLK DQS_ALIGNED_X2 USER_DEFINED DELAYG DELAYF DEL_VALUE Sets delay value when DEL_MODE...

Page 67: ...DDRDLL Attributes Attribute Description Values Default FORCE_MAX_DELAY Bypass DLL locking procedure at low frequency YES NO NO Note When Fin is 30 MHz The software sets Force_max_delay to YES DDRDLL...

Page 68: ...Primitives The ECP5 and ECP5 5G device IDDR ODDR modules support 2 1 4 1 and 7 1 gearing modes on the left and right sides only IDDR ODDR modules on the top and bottom for non SERDES parts only suppo...

Page 69: ...e Table 8 10 IDDRX2F Port List Port I O Description D I DDR data input ECLK I Fast Edge Clock SCLK I Primary Clock input divide by 2 of ECLK RST I Reset to DDR registers ALIGNWD I This signal is used...

Page 70: ...tput configurations 8 9 1 ODDRX1F This primitive is used to transmit Generic DDR with 1x gearing D0 D1 SCLK RST Q ODDRX1F Figure 8 8 ODDRX1F Table 8 12 ODDRX1F Port List Port I O Description D0 D1 I P...

Page 71: ...coming DQS signal by 90 DQSBUF receives a delay code from DDRDLL and shifts the signal accordingly There is one DQSBUF block for every 16 I O The DQSBUF should be used when the DQS clock tree is used...

Page 72: ...L READ 1 0 ECLK WRPNTR 2 0 RDPNTR 2 0 SCLK RST DYNDELAY 7 0 READCLKSEL0 BURSTDET DQSW 270 READCLKSEL1 READCLKSEL2 RDLOADN RDMOVE RDDIRECTION RDCFLAG WRLOADN WRMOVE WRDIRECTION WRCFLAG PAUSE Figure 8 1...

Page 73: ...IFIFO module DATAVALID O Signal indicating start of valid data BURSTDET O Burst Detect indicator Table 8 16 DQSBUFM Attributes Attribute Description Values Default DELAY DQS_LI_DEL_ADJ Sign bit for RE...

Page 74: ...DR3 memory interface SCLK D Q0 Q1 RST ECLK Q2 Q3 IDDRX2DQA RDPNTR 2 0 WRPNTR 2 0 DQSR90 QWL Figure 8 12 IDDRX2DQA Primitive Table 8 18 DQSBUF Port List Port I O Description D I DDR data input RST I Re...

Page 75: ...DRX2DQA This primitive is used to generate DQ data output for DDR2 with x2 gearing and for DDR3 memory interface D0 D1 SCLK RST Q ODDRX2DQA D2 D3 ECLK DQSW270 Figure 8 13 ODDRX2DQA Table 8 20 ODDRX2DQ...

Page 76: ...RST I Reset input Q O DDR data output on both edges of DQSW 8 15 Memory Output DDR Primitives for Tristate Output Control The following are the primitives used to implement tristate control for the o...

Page 77: ...y T1 ECLK I ECLK input 2x speed of SCLK DQSW270 I Clock that is 90 ahead of the clock used to generate the DQS output SCLK I SCLK input RST I Reset input Q O Tristate output 8 16 Memory Output DDR Pri...

Page 78: ...C Needed to tolerate large skew between stop and reset input Yes MEM_SYNC Needed to avoid issues on DDR memory bus and update code in operation without interrupting interface operation Yes 7 1 LVDS Bi...

Page 79: ...CLKDIV READY O Indicate that startup is finished and RX circuit is ready to operate 9 1 2 RX_SYNC This module is needed to startup RX Aligned interfaces with 2x gearing STOP DLL_LOCK FREEZE UDDCNTLN...

Page 80: ...low speed continuously running clock For example oscillator clock RST I Active high reset to this sync circuit When RST 1 STOP 0 FREEZE 0 UDDCNTLN 1 DLL_REEST 1 DDR_RESET 1 READY 0 PAUSE 0 DLL_LOCK I...

Page 81: ...ndow for the clock word and data words The PLL phase rotation goes through all 16 phases The PLL s high speed output is used to sample RX input clock Transitions are detected on the second IDDR71 outp...

Page 82: ...hange without notice 82 FPGA TN 02035 1 3 Table 9 7 MIPI_FILTER Port Description Port I O Description FILTER_CLK I Clock used to drive digital filter Min freq 100 MHz Recommendation is to use internal...

Page 83: ...claimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are s...

Page 84: ...Speed DDR Interfaces section Memory DDR Primitives Changed LPDDR2 and LPDDR3 Clock values in Table 8 17 Revision 1 1 November 2015 Section Change Summary All Added support for ECP5 5G Changed documen...

Page 85: ...s patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and informa...

Page 86: ...www latticesemi com...

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