CrossLink Programming and Configuration Usage Guide
Technical Note
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. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-TN-02014-1.2
4.1.
Power-up Sequence
Power must be applied to CrossLink for it to operate. For a short period of time, as the voltages applied to the system
rise, the FPGA will have an indeterminate state. Upstream sources should not enable output until CrossLink has
completed its configuration to ensure that CrossLink is operating in a known state.
As power continues to ramp, a Power On Reset (POR) circuit inside the FPGA becomes active. The POR circuit, once
active, makes sure the external I/O pins are in a high-impedance state. It also monitors the V
CC
, V
CCIO0
and V
CCAUX
input
CrossLink Family Data Sheet (FPGA-DS-02007)
for exact Power On Voltage levels.
When POR conditions are met, the POR circuit releases an internal reset strobe, allowing the device to begin its
initialization process. CrossLink drives CDONE LOW.
4.2.
Initialization
CrossLink enters the memory initialization phase immediately after the Power On Reset circuit drives the CDONE status
pin LOW. The purpose of the initialization state is to clear all of the SRAM memory inside the FPGA.
The FPGA remains in the initialization state until the CRESETB pin is deasserted (HIGH) or until after the SSPI/SI
2
C
activation code is received.
4.3.
Configuration Ports Default Behavior and Arbitration
During power up or when CRESETB pin toggles from LOW to HIGH or REFRESH command execution, the Configuration
Logic puts the device into master auto boot mode. The device boots either from internal NVCM or external SPI boot
PROM, if the CRESETB pin is “HIGH”, after a brief internal initialization time.
The blank CrossLink device employs the default BOOT_UP_SEQUENCE for Dual Boot configuration mode with the
NVCM-EXT. The configuration engine first attempts to boot from the NVCM. If it fails due to blank NVCM, it tries to
boot from the external SPI Flash using the MSPI configuration mode as a default behavior.
Holding CRESETB LOW postpones the master auto booting event, and allows the slave configuration ports (Slave SPI or
Slave I
2
C) to detect a ‘Slave Active’ condition. An external SPI Master or I
2
C Master needs to write the Activation Key to
the FPGA while CRESETB is held LOW and within 9.5 ms from V
CC
min during power up. This means that the slave port is
addressed, the Slave Configuration Port Activation Key (as listed in
) is sent in, and the Activation Key matches
the pre-defined key code. If any slave port declares active before CRESETB is released HIGH, the device is activated for
slave configuration. If no slave port is declared active before the CRESETB pin is released HIGH, the device performs
master auto booting sequence.
Table 4.1. Slave Configuration Port Activation Key
Active Key
Header
Data
Slave SPI Port
Dummy Bytes
1
32’HA4C6F48A
I
2
C Port
Slave I
2
C Port Address Write
2
32’HA4C6F48A
Notes
:
1.
The number of dummy bytes should be at least 1.
2.
The slave I
2
C address could be either 7 bits or 10 bits address.
The I
2
C and SPI pins are intentionally shared (MCK/SPI_SCK/SDA and CSN/SPI_SS/SCL) in such manner to prevent
unintentional activation of either port. For example, a valid I
2
C interface can never inadvertently activate the SPI port
and vice versa.
