CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
96
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FPGA-TN-02245-0.81
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The threshold voltage can be configured as 125 mV or 180 mV, by accessing the bit[1] of PMA Control Register 0 [PMA
reg00]. The loss of signal condition is defined in
. After reset, if TranDet is not asserted, it means no transition
exceeding the threshold voltage is detected at RxDP/RxDN. If TranDet is asserted, it means at least one transition
exceeding threshold voltage is detected at RxDP/RxDN.
The signal detector output can be found by accessing the bit[2] of PMA Status Register [PMA reg127].
Table 9.1. Loss of Signal Conditions
Threshold Voltage
Loss of Signal Conditions
125 mV
Rx differential amplitude less than 125 mV.
180 mV
Rx differential amplitude less than 180 mV.
Loss of Lock
Both Tx PLLs and CDR PLLs have the loss-of-lock detectors for PMA debug purpose.
If the Tx PLL loses lock, the loss-of-lock for the PLL is asserted and remains asserted until the PLL reacquires lock state.
When the PLL loses lock, it is likely to be caused by a reference clock problem. The Tx PLL loss-of-lock detector output
can be found by accessing the bit[4] of PMA Status Register [PMA reg127].
For CDR PLLs, there are two steps to get the lock state:
Frequency lock or lock with reference to reference clock, is a frequency lock operation whereby CDR PLL locks to
the reference clock through the Phase Frequency Detector (PFD) operation. Sampling clock at the receiver is not
aligned to the center of the data eye during this step.
Phase lock or lock with reference to input bitstream, is a phase lock operation whereby CDR PLL acquires phase
and small frequency deviation lock to the bitstream. Sampling clock at the receiver is aligned to the center of the
data eye after this step. It is imperative that the bitstream be valid upon entering phase lock. There are two further
steps for the phase lock:
Coarse phase lock, which has higher range of frequency acquisition (
±
5000 ppm of static frequency
difference). This step is always a transient step before embarking on to fine phase lock.
Fine phase lock, which has a lower range of frequency acquisition (
±
300 ppm static frequency difference).
Note that fine phase lock can acquire to spread spectrum modulated signals (dynamic frequency difference)
when the slow moving frequency of the input intersects the current frequency of CDR PLL. Thereafter, fine
phase lock continues to track spread spectrum modulation barring abrupt frequency jumps requiring
reacquisition in coarse phase lock.
The CDR PLL loss-of-lock detector output can be found by accessing the bit[3] and bit[5] of PMA Status Register [PMA
reg127].
shows the typical duration time for each lock step.
Figure 9.6. CDR PLL Locking Flow
Table 9.2. Typical Duration Time for Each Lock Step
Description
Frequency Lock
Coarse Phase Lock
Fine Phase Lock
Duration when training
15 µs
0.5 µs – 50 µs
0.25 µs – 25 µs
Duration when relocking
15 µs
0.5 µs
0.25 µs
