POWER AMPLIFIER HEATSINK ASSEMBLY
TSM21Q-365 Rev 0 July 17, 2009
PA Assembly
27
1 FUNCTIONAL
DESCRIPTION:
The Power Amplifier heatsink assembly consists of a preamplifier driving a four-way power splitter, four 250W
FET amplifiers, a four-way power combiner. A full-size heatsink provides the cooling for the active devices. It is
designed for High Band 174 - 230 MHz television systems, and provides power gain of approximately 15 - 16 dB,
with 1 kW peak sync visual or 600 W aural output. The module can provide upwards of 200W of average digital
power when used with appropriate predistortion.
2
RF PREAMPLIFIER
High Band preamps 10A1453G1, used in higher powered transmitter service, have a type MWA130 instead of an
MWA330 for U4. Specified gain of an MWA130 is approximately 12dB.
At the output of U2, a match to 50
Ω
is provided by C12 and the device lead inductance. These together create a
low pass matching network in boards where a type CA2885 amplifier is used; conversely a type MHW6185 device
characteristics give it a wideband match to 50
Ω
therefore no special output matching is necessary, and C12 is not
present.
U3 is a voltage regulator pro24 V to the preamplifier stage(s).
3
POWER AMPLIFIER:
.
The output amplifier consists of a single, source grounded, N-channel, insulated gate Field Effect Transistors (FETs)
packaged in a single case and operating Class AB in a push-pull configuration. Because these FETs are
"enhancement mode" devices, they require a positive gate-to-source bias voltage on each gate to cause
source-drain conduction. The quiescent Class AB idling bias current is set independently for each half. The
threshold gate voltage required to produce this idling current is typically may vary between 2V and 5V. Gate voltage
thresholds in FETs also are temperature sensitive, so thermal compensation is provided by thermistor elements RT1
and RT2. Bias current is set to 500mA per half of the device for analog operation and 750mA per half for digital
operation.
Gate bias is supplied from an adjustable voltage divider from the +39 V regulated bias rail. Resistors R1, R2, R3,
R4 provide gate bias for one half of the amplifier; R5, R6, R7, R8 provide bias for the other half.
The RF input signal is applied to balun T1/L1 to provide two signals 180
°
out of phase. These signals are stepped
down to match the low input impedance of the FET through a double L-
π
-network consisting of C1, C2, L2, L3, C7,
and the gate capacitances of the FET, and then applied to the gates. The gate input impedance at the operating
frequency is very low by comparison with the values of R3 and R6, so these resistors have little or no effect at RF.
R3 and R6 provide a DC path for bias, and provide loading at lower frequencies in order to assist in maintaining
amplifier stability. The choice of C4 and C5 values, and their internal equivalent series inductances, also ensures
effective bypassing at all frequencies.
The output matching double
π
-network, consisting of inductors L4 thru L10, and capacitances C12 thru C15, tunes
out the FET drain capacitance and transforms the very low output impedance of the FET to 12.5 ohms. The two
antiphase output signals, Push and Pull, are combined in balun T2, L11.
DC is applied to the drains through L4, L5 for the first half, and L6, L7 for the other half. L5 and L6 are also short
sections of microstrip transmission line which transform the apparent RF impedances of L4 and L7 to more effective
values as seen by the FET. RF and lower frequencies are bypassed with C3, C8, C9, and C6, C10, C11.
These groups of capacitors are selected in value and for their internal equivalent series inductances so that they will
be an effective bypass at all frequencies of interest including video, to assist in maintaining amplifier stability.
Towards this objective of stability: inductance L9, in addition to resonating with the FET output capacitance in the
